Josep Torrellas

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Jose RenauProcessor of Computer Science Engineering, UCSCVerified email at ucsc.edu
Luis CezeProfessor of Computer Science and Engineering, University of WashingtonVerified email at cs.washington.edu
Smruti R. SarangiComputer Science, IIT DelhiVerified email at cse.iitd.ac.in
Radu TeodorescuThe Ohio State UniversityVerified email at cse.ohio-state.edu
Milos PrvulovicProfessor of Computer Science, Georgia TechVerified email at cc.gatech.edu
Michael HuangUniversity of RochesterVerified email at rochester.edu
Pablo MontesinosAppleVerified email at apple.com
Lawrence RauchwergerProfessor of Computer Science, University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Zheng ZhangProfessor of Computer Science and Engineering, NYU ShanghaiVerified email at nyu.edu
Wonsun AhnUniversity of PittsburghVerified email at cs.pitt.edu
Maria GarzaranResearch assistant professor, University of Illinois at Urbana-ChampaignVerified email at uiuc.edu
Yuanyuan ZhouUniversity of California, San DiegoVerified email at eng.ucsd.edu
John HennessyStanford UniversityVerified email at stanford.edu
Calin CascavalGoogleVerified email at cascaval.us
Ulya R. KarpuzcuAssociate Professor of Electrical and Computer Engineering, University of Minnesota, Twin-CitiesVerified email at umn.edu
Nam Sung KimProfessor and Fellow of ACM and IEEE, Electrical and Computer Engineering, University of IllinoisVerified email at illinois.edu
Aditya AgrawalSenior Software Engineer, Google BrainVerified email at illinois.edu
Pedro TrancosoDepartment of Computer Science and Engineering, Chalmers University of TechnologyVerified email at chalmers.se
Yan SolihinUniversity of Central FloridaVerified email at ucf.edu
Jaejin LeeDept. of Compter Science and Engineering, Seoul National UniversityVerified email at snu.ac.kr

Josep Torrellas

Professor of Computer Science, University of Illinois Urbana-Champaign

Verified email at illinois.edu - Homepage

Computer architecture parallel computing shared-memory architectures


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VARIUS: A model of process variation and resulting timing errors for microarchitects SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008	472	2008
A chip-multiprocessor architecture with speculative multithreading V Krishnan, J Torrellas IEEE Transactions on Computers 48 (9), 866-880, 1999	424	1999
Variation-aware application scheduling and power management for chip multiprocessors R Teodorescu, J Torrellas ACM SIGARCH computer architecture news 36 (3), 363-374, 2008	409	2008
Bulk disambiguation of speculative threads in multiprocessors L Ceze, J Tuck, J Torrellas, C Cascaval ACM SIGARCH Computer Architecture News 34 (2), 227-238, 2006	407	2006
ReVive: Cost-effective architectural support for rollback recovery in shared-memory multiprocessors M Prvulovic, Z Zhang, J Torrellas ACM SIGARCH Computer Architecture News 30 (2), 111-122, 2002	339	2002
FlexRAM: Toward an advanced intelligent memory system Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999	325	1999
FlexRAM: Toward an advanced intelligent memory system Y Kang, W Huang, SM Yoo, D Keen, Z Ge, V Lam, P Pattnaik, J Torrellas Computer Design (ICCD), 1999 IEEE International Conference on, 5-14, 1999	325	1999
POSH: a TLS compiler that exploits program structure W Liu, J Tuck, L Ceze, W Ahn, K Strauss, J Renau, J Torrellas Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006	310	2006
False sharing and spatial locality in multiprocessor caches J Torrellas, HS Lam, JL Hennessy IEEE Transactions on Computers 43 (6), 651-663, 1994	309	1994
Proving program termination B Cook, A Podelski, A Rybalchenko Communications of the ACM 54 (5), 88-98, 2011	301*	2011
Characterizing and predicting program behavior and its variability E Duesterwald, C Cascaval, S Dwarkadas 2003 12th International Conference on Parallel Architectures and Compilation …, 2003	300	2003
BulkSC: Bulk enforcement of sequential consistency L Ceze, J Tuck, P Montesinos, J Torrellas Proceedings of the 34th annual international symposium on Computer …, 2007	297	2007
Cherry: Checkpointed early resource recycling in out-of-order microprocessors J Martínez, J Renau, M Huang, M Prvulovic, J Torrellas Intl. Symp. on Microarchitecture (MICRO), 2002	291	2002
Architectural support for scalable speculative parallelization in shared-memory multiprocessors M Cintra, JF Martínez, J Torrellas Proceedings of the 27th annual international symposium on Computer …, 2000	278	2000
Facelift: Hiding and slowing down aging in multicores A Tiwari, J Torrellas 2008 41st IEEE/ACM International Symposium on Microarchitecture, 129-140, 2008	276	2008
Delorean: Recording and deterministically replaying shared-memory multiprocessor execution ef? ciently P Montesinos, L Ceze, J Torrellas ACM SIGARCH Computer Architecture News 36 (3), 289-300, 2008	265	2008
Speculative synchronization: Applying thread-level speculation to explicitly parallel applications JF Martinez, J Torrellas ACM SIGOPS Operating Systems Review 36 (5), 18-29, 2002	257	2002
Positional adaptation of processors: application to energy reduction MC Huang, J Renau, J Torrellas 30th Annual International Symposium on Computer Architecture, 2003 …, 2003	250	2003
A framework for dynamic energy efficiency and temperature management M Huang, J Renau, SM Yoo, J Torrellas Proceedings of the 33rd annual ACM/IEEE international symposium on …, 2000	216	2000
Using a user-level memory thread for correlation prefetching Y Solihin, J Lee, J Torrellas Proceedings 29th Annual International Symposium on Computer Architecture …, 2002	204	2002

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