| Cortico–basal ganglia circuit mechanism for a decision threshold in reaction time tasks CC Lo, XJ Wang Nature neuroscience 9 (7), 956-963, 2006 | 586 | 2006 |
| Common scale-invariant patterns of sleep–wake transitions across mammalian species CC Lo, T Chou, T Penzel, TE Scammell, RE Strecker, HE Stanley, ... Proceedings of the National Academy of Sciences 101 (50), 17545-17548, 2004 | 277 | 2004 |
| 24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019 | 270 | 2019 |
| 15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020 | 221 | 2020 |
| Dynamics of sleep-wake transitions during sleep CC Lo, LAN Amaral, S Havlin, PC Ivanov, T Penzel, JH Peter, HE Stanley Europhysics Letters 57 (5), 625, 2002 | 211 | 2002 |
| Connectomics-based analysis of information flow in the Drosophila brain CT Shih, O Sporns, SL Yuan, TS Su, YJ Lin, CC Chuang, TY Wang, ... Current Biology 25 (10), 1249-1258, 2015 | 196 | 2015 |
| 15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ... 2020 IEEE international solid-state circuits conference-(ISSCC), 246-248, 2020 | 194 | 2020 |
| 15.2 A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020 | 161 | 2020 |
| 16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021 | 150 | 2021 |
| Proactive inhibitory control and attractor dynamics in countermanding action: a spiking neural circuit model CC Lo, L Boucher, M Paré, JD Schall, XJ Wang Journal of Neuroscience 29 (28), 9059-9071, 2009 | 144 | 2009 |
| A 28nm 1Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6 ns latency, 1241GOPS and 37.01 TOPS/W for 8b-MAC operations for edge-AI devices PC Wu, JW Su, YL Chung, LY Hong, JS Ren, FC Chang, Y Wu, HY Chen, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 90 | 2022 |
| An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4-21.6 TOPS/W for edge-AI devices JM Hung, YH Huang, SP Huang, FC Chang, TH Wen, CI Su, WS Khwa, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 74 | 2022 |
| A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices JM Hung, CX Xue, HY Kao, YH Huang, FC Chang, SP Huang, TW Liu, ... Nature Electronics 4 (12), 921-930, 2021 | 61 | 2021 |
| Modulation of the disturbed motor network in dystonia by multisession suppression of premotor cortex YZ Huang, CS Lu, JC Rothwell, CC Lo, WL Chuang, YH Weng, SC Lai, ... Public Library of Science 7 (10), e47574, 2012 | 56 | 2012 |
| Asymmetry and basic pathways in sleep-stage transitions CC Lo, RP Bartsch, PC Ivanov Europhysics letters 102 (1), 10008, 2013 | 52 | 2013 |
| Coupled symmetric and asymmetric circuits underlying spatial orientation in fruit flies TS Su, WJ Lee, YC Huang, CT Wang, CC Lo Nature communications 8 (1), 139, 2017 | 50 | 2017 |
| A 22nm 4Mb STT-MRAM data-encrypted near-memory computation macro with a 192GB/s read-and-decryption bandwidth and 25.1-55.1 TOPS/W 8b MAC for AI operations YC Chiu, CS Yang, SH Teng, HY Huang, FC Chang, Y Wu, YA Chien, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 178-180, 2022 | 49 | 2022 |
| Ai edge devices using computing-in-memory and processing-in-sensor: from system to device TH Hsu, YC Chiu, WC Wei, YC Lo, CC Lo, RS Liu, KT Tang, MF Chang, ... 2019 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2019 | 39 | 2019 |
| A 22nm 832Kb hybrid-domain floating-point SRAM in-memory-compute macro with 16.2-70.2 TFLOPS/W for high-accuracy AI-edge devices PC Wu, JW Su, LY Hong, JS Ren, CH Chien, HY Chen, CE Ke, HM Hsiao, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 126-128, 2023 | 34 | 2023 |
| Two-way transpose multibit 6T SRAM computing-in-memory macro for inference-training AI edge chips JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ... IEEE Journal of Solid-State Circuits 57 (2), 609-624, 2021 | 33 | 2021 |
