Follow
Karthik Raman
Title
Cited by
Cited by
Year
Intel Xeon Phi processor high performance programming: knights landing edition
J Jeffers, J Reinders, A Sodani
Morgan Kaufmann, 2016
4272016
Large-scale GW calculations on pre-exascale HPC systems
M Del Ben, FH da Jornada, A Canning, N Wichmann, K Raman, ...
Computer Physics Communications 235, 187-195, 2019
472019
Increasing molecular dynamics simulation rates with an 8-fold increase in electrical power efficiency
WM Brown, A Semin, M Hebenstreit, S Khvostov, K Raman, SJ Plimpton
SC'16: Proceedings of the International Conference for High Performance …, 2016
112016
Chapter 3-Better concurrency and SIMD on HBM
JW Poulsen, P Berg, K Raman
High Performance Parallelism Pearls: Multicore and Many-core Programming …, 2014
92014
Optimizing memory bandwidth on stream triad
K Raman
Intel Corporation 30, 32, 2013
92013
Instruction and logic for adaptive dataset priorities in processor caches
KA Doshi, K Raman, CJ Hughes
US Patent 9,405,706, 2016
82016
High performance computing systems
SA Jarvis, SA Wright, SD Hammond
Proceedings of the 4th Internation Performance Modeling, Benchmarking, and …, 2013
82013
Enhancing application performance using heterogeneous memory architectures on a many-core platform
S Li, K Raman, R Sasanka
2016 International Conference on High Performance Computing & Simulation …, 2016
72016
Optimizing memory bandwidth in knights landing on stream triad
K Raman
Available Online, 2016
72016
Accelerating tensorflow on modern intel architectures
E Ould-Ahmed-Vall, M Abuzaina, MF Amin, J Bobba, RS Dubtsov, ...
First International Workshop on Architectures for Intelligent Machines, 2017
52017
Optimizing excited-state electronic-structure codes for Intel Knights Landing: A case study on the BerkeleyGW software
J Deslippe, FH da Jornada, D Vigil-Fowler, T Barnes, N Wichmann, ...
High Performance Computing: ISC High Performance 2016 International …, 2016
52016
Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline
WM Brown, R Schulz, K Raman
US Patent 10,409,601, 2019
42019
Improving achieved memory bandwidth from C++ codes on Intel® Xeon Phi™ Processor (Knights Landing)
K Raman, T Deakin, J Price, S McIntosh-Smith
IXPUG Spring Meeting, 2017
42017
Optimizing performance of roms on intel xeon phi
G Bhaskaran, P Gaurav
Procedia Computer Science 51, 2854-2858, 2015
42015
Fusion PIC code performance analysis on the cori KNL system
T Koskela, J Deslippe, B Friesen, R Karthik
32018
Better Concurrency and SIMD On The HIROMB-BOOS-MODEL (HBM) 3D Ocean Code
JW Poulsen, P Berg, K Raman
High Performance Parallelism Pearls: Multicore and Many-core Programming …, 2014
32014
Dynamically predict and enhance energy efficiency
K Raman, W Brown, RK Malladi, A Semin
US Patent App. 15/449,696, 2018
22018
Apparatuses, methods, and systems for mixing vector operations
RKV Malladi, E Ould-Ahmed-Vall, R Valentine, K Raman
US Patent App. 15/277,963, 2018
22018
Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline
WM Brown, R Schulz, K Raman
US Patent 12,079,628, 2024
2024
Harmonie-Arome on AWS
JW Poulsen, X Yang, E Whelan, K Raman
EMS2022, 2022
2022
The system can't perform the operation now. Try again later.
Articles 1–20