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Mallika Rathore
Mallika Rathore
Hardware Engineer, Google
Verified email at alumni.stonybrook.edu
Title
Cited by
Cited by
Year
A novel static d-flip-flop topology for low swing clocking
M Rathore, W Liu, E Salman, C Sitik, B Taskin
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, 301-306, 2015
92015
Error probability models for voltage-scaled multiply-accumulate units
M Rathore, P Milder, E Salman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (7 …, 2020
82020
Error probability models to facilitate approximate computing in TFET based circuits
M Rathore, E Salman
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
22018
Precision and Performance-Aware Voltage Scaling in DNN Accelerators
M Rathore, P Milder, E Salman
Proceedings of the Great Lakes Symposium on VLSI 2023, 237-242, 2023
2023
Exploring the Accuracy vs Energy Efficiency Trade-Offs in Error-Aware Low Voltage Dnn Accelerators
M Rathore
State University of New York at Stony Brook, 2021
2021
Design and Analysis of Custom Clock Buffers and a D Flip-Flop for Low Swing Clock Distribution Networks
M Rathore
State University of New York at Stony Brook, 2014
2014
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Articles 1–6