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Joseph Sharkey
Joseph Sharkey
High Peaks Cyber
Verified email at highpeakscyber.com
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Cited by
Cited by
Year
M-sim: a flexible, multithreaded architectural simulation environment
J Sharkey, D Ponomarev, K Ghose
Techenical report, Department of Computer Science, State University of New …, 2005
1142005
Behavioral analytics driven host-based malicious behavior and data exfiltration disruption
KR Swidowski, KA Zaffarano, JM Syversen, JJ Sharkey, JJ Danahy, ...
US Patent App. 14/602,011, 2015
712015
M-Sim: A flexible, multi-threaded simulation environment
J Sharkey
Tech. Report CS-TR-05-DP1, Department of Computer Science, SUNY Binghamton, 2005
692005
Evaluating design tradeoffs in on-chip power management for CMPs
J Sharkey, A Buyuktosunoglu, P Bose
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
532007
Adaptive reorder buffers for SMT processors
J Sharkey, D Balkan, D Ponomarev
Proceedings of the 15th international conference on Parallel architectures …, 2006
402006
Methods for securing a processing system and devices thereof
JJ Sharkey, RP Quinn
US Patent App. 12/973,548, 2011
342011
Efficient instruction schedulers for SMT processors
JJ Sharkey, DV Ponomarev
The Twelfth International Symposium on High-Performance Computer …, 2006
292006
Efficient instruction schedulers for SMT processors
JJ Sharkey, DV Ponomarev
The Twelfth International Symposium on High-Performance Computer …, 2006
292006
Instruction packing: reducing power and delay of the dynamic scheduling logic
JJ Sharkey, DV Ponomarev, K Ghose, O Ergin
Proceedings of the 2005 international symposium on Low power electronics and …, 2005
272005
Selective writeback: Reducing register file pressure and energy consumption
D Balkan, J Sharkey, D Ponomarev, K Ghose
IEEE transactions on very large scale integration (VLSI) systems 16 (6), 650-661, 2008
262008
Trade-offs in transient fault recovery schemes for redundant multithreaded processors
J Sharkey, N Abu-Ghazeleh, D Ponomarev, K Ghose, A Aggarwal
International Conference on High-Performance Computing, 135-147, 2006
182006
SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency
D Balkan, J Sharkey, D Ponomarev, K Ghose
Proceedings of the 15th international conference on Parallel architectures …, 2006
182006
Instruction packing: Toward fast and energy-efficient instruction scheduling
JJ Sharkey, DV Ponomarev, K Ghose, O Ergin
ACM Transactions on Architecture and Code Optimization (TACO) 3 (2), 156-181, 2006
172006
Address-value decoupling for early register deallocation
D Balkan, J Sharkey, D Ponomarev, A Aggarwal
2006 International Conference on Parallel Processing (ICPP'06), 337-346, 2006
152006
Breaking Hardware Enforced Security with Hypervisors
J Sharkey
BlackHat USA 2016, 2016
132016
An L2-miss-driven early register deallocation for SMT processors
J Sharkey, D Ponomarev
Proceedings of the 21st annual international conference on Supercomputing …, 2007
102007
Exploiting operand availability for efficient simultaneous multithreading
JJ Sharkey, DV Ponomarev
IEEE Transactions on Computers 56 (2), 208-223, 2007
102007
Method and system for reducing an impact of malware during a booting sequence
RM Wilson, JJ Sharkey, MJ Sieffert
US Patent 8,478,974, 2013
82013
Reducing register pressure in smt processors through l2-miss-driven early register release
JJ Sharkey, J Loew, DV Ponomarev
ACM Transactions on Architecture and Code Optimization (TACO) 5 (3), 1-28, 2008
82008
Selective writeback: exploiting transient values for energy-efficiency and performance
D Balkan, J Sharkey, D Ponomarev, K Ghose
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
72006
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