| A 2.5 ppm/° C 1.05-MHz relaxation oscillator with dynamic frequency-error compensation and fast start-up time N Liu, R Agarwala, A Dissanayake, DS Truesdell, S Kamineni, ... IEEE Journal of Solid-State Circuits 54 (7), 1952-1959, 2019 | 33 | 2019 |
| An open-source framework for autonomous SoC design with analog block generation T Ajayi, S Kamineni, YK Cherivirala, M Fayazi, K Kwon, M Saligane, ... 2020 IFIP/IEEE 28th International Conference on Very Large Scale Integration …, 2020 | 29 | 2020 |
| A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V microprocessor using scalable dynamic leakage-suppression logic DS Truesdell, J Breiholz, S Kamineni, N Liu, A Magyar, BH Calhoun IEEE Solid-State Circuits Letters 2 (8), 57-60, 2019 | 21 | 2019 |
| An 85 nW IoT node-controlling SoC for MELs power-mode management and phantom energy reduction S Li, J Breiholz, S Kamineni, J Im, DD Wentzloff, BH Calhoun 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 9 | 2020 |
| MemGen: An open-source framework for autonomous generation of memory macros S Kamineni, S Gupta, BH Calhoun 2021 IEEE Custom Integrated Circuits Conference (CICC), 1-2, 2021 | 7 | 2021 |
| A 194nW energy-performance-aware loT SoC employing a 5.2 nW 92.6% peak efficiency power management unit for system performance scaling, fast DVFS and energy minimization X Liu, S Kamineni, J Breiholz, BH Calhoun, S Li 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 6 | 2022 |
| Minimal buffer insertion based low power clock tree synthesis for 3D integrated circuits K Sumanth Kumar, J Reuben Journal of Circuits, Systems and computers 25 (11), 1650142, 2016 | 5 | 2016 |
| AuxcellGen: A framework for autonomous generation of analog and memory unit cells S Kamineni, A Sharma, R Harjani, SS Sapatnekar, BH Calhoun 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 4 | 2023 |
| A Bluetooth-Low-Energy Backchannel Receiver Employing a Discrete-Time Differentiator-Based Coherent GFSK Demodulation O Abdelatty, A Alghaihab, YK Cherivirala, S Kamineni, B Calhoun, ... 2021 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 239-242, 2021 | 4 | 2021 |
| Fully autonomous mixed signal SoC design & layout generation platform T Ajayi, Y Cherivirala, K Kwon, S Kamineni, M Saligane, M Fayazi, ... IEEE, 2020 | 4 | 2020 |
| Multiple combined write-read peripheral assists in 6T FinFET SRAMs for low-VMIN IoT and cognitive applications A Banerjee, S Kamineni, BH Calhoun Proceedings of the International Symposium on Low Power Electronics and …, 2018 | 3 | 2018 |
| A Sub-W Energy-Performance-Aware IoT SoC With a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization X Liu, S Kamineni, J Breiholz, BH Calhoun, S Li IEEE Journal of Solid-State Circuits, 2024 | 1 | 2024 |
| Fully-Autonomous SoC Synthesis Using Customizable Cell-Based Analog and Mixed-Signal Circuits Generation T Ajayi, S Kamineni, M Fayazi, YK Cherivirala, K Kwon, S Gupta, W Duan, ... VLSI-SoC: Design Trends: 28th IFIP WG 10.5/IEEE International Conference on …, 2021 | | 2021 |
| Hot Chips 2020 Posters F Elsabbagh, B Tine, A Chawda, W Gulian, Y Feng, P Roshan, E Lyons, ... 2020 IEEE Hot Chips 32 Symposium (HCS), 1-159, 2020 | | 2020 |
| ISSCC 2022/SESSION 13/DIGITAL TECHNIQUES FOR CLOCKING, VARIATION TOLERANCE AND POWER MANAGEMENT/13.8 X Liu, S Kamineni, J Breiholz, BH Calhoun, S Li | | |
| A 6–140-nW 11 Hz–8.2-kHz DVFS RISC-V Microprocessor Using Scalable Dynamic Leakage-Suppression Logic DS Truesdell, J Breiholz, S Kamineni, N Liu, A Magyar, BH Calhoun | | |
Benton CalhounProfessor of Electrical and Computer Engineering, University of VirginiaVerified email at virginia.edu
