Yongseok Cheon
Title
Cited by
Cited by
Year
Power-aware placement
Y Cheon, PH Ho, AB Kahng, S Reda, Q Wang
Proceedings of the 42nd annual Design Automation Conference, 795-800, 2005
1592005
Method and apparatus for generating a variation-tolerant clock-tree for an integrated circuit chip
Y Cheon, PH Ho
US Patent 7,546,567, 2009
372009
Design hierarchy-guided multilevel circuit partitioning
Y Cheon, MDF Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2003
182003
Method and apparatus for reducing power consumption in an integrated circuit chip
PH Ho, Y Cheon, Q Wang
US Patent 7,257,782, 2007
172007
A min-cost flow based detailed router for FPGAs
S Lee, Y Cheon, MDF Wong
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
172003
Stable multiway circuit partitioning for eco
Y Cheon, S Lee, MDF Wong
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
92003
Method and apparatus for partitioning an integrated circuit chip
PH Ho, Y Cheon
US Patent 7,260,802, 2007
72007
Crowdedness-balanced multilevel partitioning for uniform resource utilization
Y Cheon, MDF Wong
Proceedings of the 2005 Asia and South Pacific Design Automation Conference …, 2005
22005
Multilevel circuit partitioning for computer-aided VLSI design
Y Cheon
The University of Texas at Austin, 2004
22004
Clock tree synthesis for low power and low susceptibility to variation
Y Cheon, PH Ho, W Hou, Y Liu, D Wang
2007 7th International Conference on ASIC, 1333-1333, 2007
12007
Power-Aware Placement
ATG Synopsys, Y Cheon, PH Ho, R Damiano
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