| Performance evaluation of gate engineered InAs–Si heterojunction surrounding gate TFET M Sathishkumar, TSA Samuel, K Ramkumar, IV Anand, SB Rahi Superlattices and Microstructures 162, 107099, 2022 | 14 | 2022 |
| Modeling and simulation of a dual-material asymmetric heterodielectric-gate TFET I Vivek Anand, TS Arun Samuel, P Vimala Journal of Computational Electronics 19, 1450-1462, 2020 | 6 | 2020 |
| Design of combinational logic circuits for low power reversible logic circuits in quantum cellular automata IV Anand, A Kamaraj International Conference on Information Communication and Embedded Systems …, 2014 | 6 | 2014 |
| Design of low power combinational circuits using reversible logic and realization in quantum cellular automata A Kamaraj, IV Anand, P Marichamy International Journal of Innovative Research in Science, Engineering and …, 2014 | 6 | 2014 |
| Modelling and simulation of hetero-dielectric surrounding gate TFET IV Anand, TSA Samuel, P Vimala, A Shenbagavalli journal of Nano research 62, 47-58, 2020 | 4 | 2020 |
| Influence of trap carriers in SiO2/HfO2 stacked dielectric cylindrical gate tunnel fet IV Anand, TSA Samuel, VN Ramakrishnan, K Ram Kumar Silicon, 1-12, 2021 | 3 | 2021 |
| Design ff Low Power Multiplier Unit using Wallace Tree Algorithm R Krishnaveni, B Sivaranjani, PS Priya, M Sathishkumar, IV Anand | 2 | 2020 |
| Design and implementation of VLIW DSP processors for high ended embedded based systems A Karthihaa, S Karthika, KM Priyadharshini, L Sivasankari, IV Anand, ... AIP Conference Proceedings 2378 (1), 2021 | 1 | 2021 |
| Investigation of tri-gate hetero-junction stacked dielectric transistor for improved ON-current IV Anand, TSA Samuel, P Vimala, VN Ramakrishnan Materials Today: Proceedings 45, 4026-4035, 2021 | 1 | 2021 |
| Design of pipelined MIPS Processor with Cache controller using Verilog Implementation R Deepika, SM Gopika Priyadharsini, M Malini Praba, M Muthu Malar, ... NVEO-NATURAL VOLATILES & ESSENTIAL OILS Journal| NVEO, 5220–5229-5220–5229, 2021 | | 2021 |
| IMPLEMENTATION OF FLOATING POINT FFT PROCESSOR WITH SINGLE PRECISION FOR REDUCTION IN POWER R Balasaraswathi, D Divya, M Harinikalayani, IVA ME, TSA Samuel | | 2020 |
