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Naveen Muralimanohar
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ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars
A Shafiee, A Nag, N Muralimanohar, R Balasubramonian, JP Strachan, ...
ACM SIGARCH Computer Architecture News 44 (3), 14-26, 2016
19872016
CACTI 6.0: A tool to model large caches
N Muralimanohar, R Balasubramonian, NP Jouppi
HP laboratories 27, 28, 2009
12052009
CACTI 5.1
S Thoziyoor, N Muralimanohar, JH Ahn, NP Jouppi
Technical Report HPL-2008-20, HP Labs, 2008
8292008
Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0
N Muralimanohar, R Balasubramonian, N Jouppi
40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007
8072007
Overcoming the challenges of crossbar resistive memory architectures
C Xu, D Niu, N Muralimanohar, R Balasubramonian, T Zhang, S Yu, Y Xie
2015 IEEE 21st international symposium on high performance computer …, 2015
3952015
Rethinking DRAM design and organization for energy-constrained multi-cores
AN Udipi, N Muralimanohar, N Chatterjee, R Balasubramonian, A Davis, ...
Proceedings of the 37th annual international symposium on Computer …, 2010
3532010
CACTI 7: New tools for interconnect exploration in innovative off-chip memories
R Balasubramonian, AB Kahng, N Muralimanohar, A Shafiee, V Srinivas
ACM Transactions on Architecture and Code Optimization (TACO) 14 (2), 1-25, 2017
3522017
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory
K Chen, S Li, N Muralimanohar, JH Ahn, JB Brockman, NP Jouppi
2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), 33-38, 2012
2482012
FREE-p: Protecting non-volatile memory against both hard and soft errors
DH Yoon, N Muralimanohar, J Chang, P Ranganathan, NP Jouppi, ...
2011 IEEE 17th International Symposium on High Performance Computer …, 2011
2462011
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems
X Dong, N Muralimanohar, N Jouppi, R Kaufmann, Y Xie
Proceedings of the conference on high performance computing networking …, 2009
2062009
CACTI 6.0: A tool to understand large caches
N Muralimanohar, R Balasubramonian, NP Jouppi
University of Utah and Hewlett Packard Laboratories, Tech. Rep 147, 2009
1862009
Simple but effective heterogeneous main memory with on-chip memory controller support
X Dong, Y Xie, N Muralimanohar, NP Jouppi
SC'10: Proceedings of the 2010 ACM/IEEE International Conference for High …, 2010
1842010
Interconnect-aware coherence protocols for chip multiprocessors
L Cheng, N Muralimanohar, K Ramani, R Balasubramonian, JB Carter
ACM SIGARCH Computer Architecture News 34 (2), 339-351, 2006
1622006
Understanding the trade-offs in multi-level cell ReRAM memory design
C Xu, D Niu, N Muralimanohar, NP Jouppi, Y Xie
Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013
1572013
Interconnect design considerations for large nuca caches
N Muralimanohar, R Balasubramonian
ACM SIGARCH Computer Architecture News 35 (2), 369-380, 2007
1372007
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems
AN Udipi, N Muralimanohar, R Balsubramonian, A Davis, NP Jouppi
ACM SIGARCH Computer Architecture News 40 (3), 285-296, 2012
1362012
Efficient data mapping and buffering techniques for multilevel cell phase-change memories
H Yoon, J Meza, N Muralimanohar, NP Jouppi, O Mutlu
ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-25, 2014
1252014
Architecting efficient interconnects for large caches with CACTI 6.0
N Muralimanohar, R Balasubramonian, NP Jouppi
IEEE micro 28 (1), 69-79, 2008
1132008
Multi-core cache hierarchies
R Balasubramonian, NP Jouppi, N Muralimanohar
Morgan & Claypool, 2011
1102011
Design trade-offs for high density cross-point resistive memory
D Niu, C Xu, N Muralimanohar, NP Jouppi, Y Xie
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
1062012
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