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Ioannis Savidis
Ioannis Savidis
Associate Professor, Drexel University
Verified email at coe.drexel.edu - Homepage
Title
Cited by
Cited by
Year
Three-dimensional integrated circuit design
VF Pavlidis, I Savidis, EG Friedman
Newnes, 2017
4172017
Closed-form expressions of 3-D via resistance, inductance, and capacitance
I Savidis, EG Friedman
IEEE Transactions on Electron Devices 56 (9), 1873-1881, 2009
2302009
An intra-chip free-space optical interconnect
J Xue, A Garg, B Ciftcioglu, J Hu, S Wang, I Savidis, M Jain, R Berman, ...
ACM SIGARCH Computer Architecture News 38 (3), 94-105, 2010
1012010
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits
I Savidis, SM Alam, A Jain, S Pozder, RE Jones, R Chatterjee
Microelectronics Journal 41 (1), 9-16, 2010
882010
Clock distribution networks for 3-D ictegrated Circuits
VF Pavlidis, I Savidis, EG Friedman
2008 IEEE Custom Integrated Circuits Conference, 651-654, 2008
782008
Electrical modeling and characterization of 3-D vias
I Savidis, EG Friedman
2008 IEEE International Symposium on Circuits and Systems, 784-787, 2008
732008
Clock distribution networks in 3-D integrated systems
VF Pavlidis, I Savidis, EG Friedman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (12 …, 2010
572010
3-D integrated heterogeneous intra-chip free-space optical interconnect
B Ciftcioglu, R Berman, S Wang, J Hu, I Savidis, M Jain, D Moore, ...
Optics express 20 (4), 4331-4345, 2012
542012
A 3-D integrated intrachip free-space optical interconnect for many-core chips
B Ciftcioglu, R Berman, J Zhang, Z Darling, S Wang, J Hu, J Xue, A Garg, ...
IEEE Photonics Technology Letters 23 (3), 164-166, 2010
372010
Protecting analog circuits with parameter biasing obfuscation
VV Rao, I Savidis
2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017
342017
Reduced overhead gate level logic encryption
K Juretus, I Savidis
2016 International Great Lakes Symposium on VLSI (GLSVLSI), 15-20, 2016
332016
Thermal analysis of oxide-confined VCSEL arrays
J Wang, I Savidis, EG Friedman
Microelectronics journal 42 (5), 820-825, 2011
292011
ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling
MK Tavana, MH Hajkazemi, D Pathak, I Savidis, H Homayoun
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
272015
Power conversion efficiency-aware mapping of multithreaded applications on heterogeneous architectures: A comprehensive parameter tuning
H Sayadi, D Pathak, I Savidis, H Homayoun
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 70-75, 2018
252018
Reducing logic encryption overhead through gate level key insertion
K Juretus, I Savidis
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1714-1717, 2016
252016
Power noise in TSV-based 3-D integrated circuits
I Savidis, S Kose, EG Friedman
IEEE Journal of Solid-State Circuits 48 (2), 587-597, 2012
242012
Thermal conduction path analysis in 3-d ics
B Vaisband, I Savidis, EG Friedman
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 594-597, 2014
192014
Smart grid on chip: Work load-balanced on-chip power delivery
D Pathak, H Homayoun, I Savidis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (9 …, 2017
162017
Securing analog mixed-signal integrated circuits through shared dependencies
K Juretus, V Venugopal Rao, I Savidis
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 483-488, 2019
142019
Mesh based obfuscation of analog circuit properties
VV Rao, I Savidis
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
132019
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