Ghassem Jaberipur
Ghassem Jaberipur
Professor of Computer Engineering, Shahid Beheshti University
Verified email at sbu.ac.ir
Title
Cited by
Cited by
Year
Coplanar full adder in quantum-dot cellular automata via clock-zone-based crossover
D Abedi, G Jaberipur, M Sangsefidi
IEEE transactions on nanotechnology 14 (3), 497-504, 2015
1612015
Improving the speed of parallel decimal multiplication
G Jaberipur, A Kaivani
IEEE Transactions on Computers 58 (11), 1539-1552, 2009
912009
Binary-coded decimal digit multipliers
G Jaberipur, A Kaivani
IET Computers & Digital Techniques 1 (4), 377-381, 2007
892007
A fully redundant decimal adder and its application in parallel decimal multipliers
S Gorgin, G Jaberipur
Microelectronics Journal 40 (10), 1471-1481, 2009
432009
Improved CMOS (4; 2) compressor designs for parallel multipliers
A Pishvaie, G Jaberipur, A Jahanian
Computers & Electrical Engineering 38 (6), 1703-1716, 2012
412012
Unified Approach to the Design of Modulo-(2^ n+/-1) Adders Based on Signed-LSB Representation of Residues
G Jaberipur, B Parhami
2009 19th IEEE Symposium on Computer Arithmetic, 57-64, 2009
402009
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems
G Jaberipur, B Parhami, M Ghodsi
IEEE Transactions on Circuits and Systems I: Regular Papers 52 (7), 1348-1357, 2005
382005
Fully redundant decimal arithmetic
S Gorgin, G Jaberipur
2009 19th IEEE Symposium on Computer Arithmetic, 145-152, 2009
352009
Decimal full adders specially designed for quantum-dot cellular automata
D Abedi, G Jaberipur
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (1), 106-110, 2017
282017
Redesigned CMOS (4; 2) compressor for fast binary multipliers
A Pishvaie, G Jaberipur, A Jahanian
Canadian Journal of Electrical and Computer Engineering 36 (3), 111-115, 2013
222013
Balanced minimal latency RNS addition for moduli set {2n−1, 2n, 2n+1}
G Jaberipur, S Nejati
2011 18th International Conference on Systems, Signals and Image Processing, 1-7, 2011
222011
Constant-time addition with hybrid-redundant numbers: Theory and implementations
G Jaberipur, B Parhami
Integration 41 (1), 49-64, 2008
222008
High-performance CMOS (4: 2) compressors
A Pishvaie, G Jaberipur, A Jahanian
International journal of electronics 101 (11), 1511-1525, 2014
212014
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
G Jaberipur, B Parhami
IET computers & digital techniques 6 (5), 259-268, 2012
212012
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic
G Jaberipur, B Parhami
IET circuits, devices & systems 1 (1), 102-110, 2007
202007
High radix signed digit number systems: representation paradigms
G JABERIPOUR, M Ghodsi
SCIENTIA IRANICA 10 (4), 383-391, 2003
202003
Weighted bit-set encodings for redundant digit sets: theory and applications
G Jaberipur, B Parhami, M Ghodsi
Conference Record of the Thirty-Sixth Asilomar Conference on Signals …, 2002
192002
A family of high radix signed digit adders
S Gorgin, G Jaberipur
2011 IEEE 20th Symposium on Computer Arithmetic, 112-120, 2011
172011
Low-power/cost RNS comparison via partitioning the dynamic range
Z Torabi, G Jaberipur
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (5 …, 2015
162015
A class of stored-transfer representations for redundant number systems
G Jaberipur, B Parhami, M Ghodsi
Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems …, 2001
162001
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