| Optimizing replication, communication, and capacity allocation in CMPs Z Chishti, MD Powell, TN Vijaykumar 32nd International Symposium on Computer Architecture (ISCA'05), 357-368, 2005 | 424 | 2005 |
| Trading off cache capacity for reliability to enable low voltage operation C Wilkerson, H Gao, AR Alameldeen, Z Chishti, M Khellah, SL Lu ACM SIGARCH computer architecture news 36 (3), 203-214, 2008 | 374 | 2008 |
| Distance associativity for high-performance energy-efficient non-uniform cache architectures Z Chishti, MD Powell, TN Vijaykumar Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003 | 296 | 2003 |
| Reducing cache power with low-cost, multi-bit error-correcting codes C Wilkerson, AR Alameldeen, Z Chishti, W Wu, D Somasekhar, S Lu Proceedings of the 37th annual international symposium on Computer …, 2010 | 293 | 2010 |
| Improving DRAM performance by parallelizing refreshes with accesses KKW Chang, D Lee, Z Chishti, AR Alameldeen, C Wilkerson, Y Kim, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 254 | 2014 |
| Energy-efficient cache design using variable-strength error-correcting codes AR Alameldeen, I Wagner, Z Chishti, W Wu, C Wilkerson, SL Lu ACM SIGARCH Computer Architecture News 39 (3), 461-472, 2011 | 222 | 2011 |
| Improving cache lifetime reliability at ultra-low voltages Z Chishti, AR Alameldeen, C Wilkerson, W Wu, SL Lu Proceedings of the 42nd Annual IEEE/ACM International Symposium on …, 2009 | 218 | 2009 |
| Usimm: the utah simulated memory module N Chatterjee, R Balasubramonian, M Shevgoor, S Pugsley, A Udipi, ... University of Utah, Tech. Rep, 1-24, 2012 | 196 | 2012 |
| Efficiently prefetching complex address patterns M Shevgoor, S Koladiya, R Balasubramonian, C Wilkerson, SH Pugsley, ... Proceedings of the 48th International Symposium on Microarchitecture, 141-152, 2015 | 191 | 2015 |
| Path confidence based lookahead prefetching J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016 | 172 | 2016 |
| DRAM refresh mechanisms, penalties, and trade-offs I Bhati, MT Chang, Z Chishti, SL Lu, B Jacob IEEE Transactions on Computers 65 (1), 108-121, 2015 | 154 | 2015 |
| Transparent hardware management of stacked dram as part of memory J Sim, AR Alameldeen, Z Chishti, C Wilkerson, H Kim 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 13-24, 2014 | 149 | 2014 |
| Sandbox prefetching: Safe run-time evaluation of aggressive prefetchers SH Pugsley, Z Chishti, C Wilkerson, P Chuang, RL Scott, A Jaleel, SL Lu, ... 2014 IEEE 20th International Symposium on High Performance Computer …, 2014 | 138 | 2014 |
| Flexible auto-refresh: Enabling scalable and energy-efficient DRAM refresh reductions I Bhati, Z Chishti, SL Lu, B Jacob Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 125 | 2015 |
| Techniques to reduce memory cell refreshes for a memory device ZA Chishti, IS Bhati, SLL Lu US Patent 9,418,723, 2016 | 92 | 2016 |
| Hardware support for thread scheduling on multi-core processors AR Alameldeen, ZA Chishti US Patent 8,276,142, 2012 | 84 | 2012 |
| Aggregated write back in a direct mapped two level memory Z Wang, CB Wilkerson, ZA Chishti US Patent 10,496,544, 2019 | 74 | 2019 |
| Adaptive cache design to enable reliable low-voltage operation AR Alameldeen, Z Chishti, C Wilkerson, W Wu, SL Lu IEEE Transactions on Computers 60 (1), 50-63, 2010 | 63 | 2010 |
| Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads R Wang, AJ Herdrich, YC Liu, HH Hum, JS Park, CJ Hughes, ... US Patent 10,817,425, 2020 | 61 | 2020 |
| Method and apparatus for using cache memory in a system that supports a low power state CB Wilkerson, AR Alameldeen, ZA Chishti, D Somasekhar, W Wu, SL Lu US Patent 8,640,005, 2014 | 58 | 2014 |
Shih-Lien Lu (Linus)Washington State Universityכתובת אימייל מאומתת בדומיין wsu.edu
