| Low-power clock branch sharing double-edge triggered flip-flop P Zhao, J McNeely, P Golconda, MA Bayoumi, RA Barcenas, W Kuang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (3), 338-345, 2007 | 123 | 2007 |
| Design of sequential elements for low power clocking system P Zhao, J McNeely, W Kuang, N Wang, Z Wang IEEE Transactions on very large scale integration (VLSI) systems 19 (5), 914-918, 2010 | 114 | 2010 |
| Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems P Zhao, JB McNeely, PK Golconda, S Venigalla, N Wang, MA Bayoumi, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (9 …, 2009 | 85 | 2009 |
| Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits W Kuang, P Zhao, JS Yuan, RF DeMara IEEE transactions on very large scale integration (VLSI) systems 18 (3), 410-422, 2009 | 51 | 2009 |
| Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits W Kuang, P Zhao, JS Yuan, RF DeMara IEEE transactions on very large scale integration (VLSI) systems 18 (3), 410-422, 2009 | 51 | 2009 |
| Soft error hardening for asynchronous circuits W Kuang, CM Ibarra, P Zhao 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI …, 2007 | 22 | 2007 |
| Teaching asynchronous design in digital integrated circuits JS Yuan, W Kuang IEEE Transactions on Education 47 (3), 397-404, 2004 | 21 | 2004 |
| Design asynchronous circuits for soft error tolerance W Kuang, E Xiao, CM Ibarra, P Zhao 2007 IEEE International Conference on Integrated Circuit Design and …, 2007 | 20 | 2007 |
| A low power domino with differential-controlled-keeper P Zhao, J McNeely, M Bayoumi, G Pradeep, K Weidong 2007 IEEE International Symposium on Circuits and Systems, 1625-1628, 2007 | 13 | 2007 |
| Low power operation using self-timed circuits and ultra-low supply voltage W Kuang, JS Yuan The 14th International Conference on Microelectronics,, 185-188, 2002 | 12 | 2002 |
| Performance analysis and optimisation of NCL self-timed rings W Kuang, JS Yuan, RF DeMara, M Hagedorn, K Fant IEE Proceedings Circuits Devices and Systems 150 (3), 167-172, 2003 | 10 | 2003 |
| Supply voltage scalable system design using self-timed circuits W Kuang, JS Yuan, A Ejnioui IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings., 161-166, 2003 | 10 | 2003 |
| A real-time attendance system using deep-learning face recognition W Kuang, A Baul | 9 | 2020 |
| A delay-insensitive FIR Filter for DSP applications W Kuang, JS Yuan, RF DeMara, D Ferguson, M Hagedorn Proc. 9th Annu. NASA Symp. VLSI Design, 135-165, 2000 | 9 | 2000 |
| Correction and comment on “An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications” W Kuang IEEE Transactions on Circuits and Systems I: Regular Papers 60 (4), 1097-1099, 2012 | 8 | 2012 |
| Correction and comment on “An adaptive resolution asynchronous ADC architecture for data compression in energy constrained sensing applications” W Kuang IEEE Transactions on Circuits and Systems I: Regular Papers 60 (4), 1097-1099, 2012 | 8 | 2012 |
| PMOS breakdown effects on digital circuits–Modeling and analysis W Kuang, L Cao, C Yu, JS Yuan Microelectronics Reliability 48 (8-9), 1597-1600, 2008 | 7 | 2008 |
| Iterative ring and power-aware design techniques for self-timed digital circuits W Kuang University of Central Florida, 2003 | 5 | 2003 |
| The Effect of Training Dataset Size on SAR Automatic Target Recognition Using Deep Learning W Kuang, W Dong, L Dong 2022 IEEE 12th International Conference on Electronics Information and …, 2022 | 4 | 2022 |
| Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance Y Bai, W Kuang 2011 14th Euromicro Conference on Digital System Design, 247-253, 2011 | 4 | 2011 |
