| Low-power and area-efficient carry select adder B Ramkumar, HM Kittur IEEE transactions on very large scale integration (VLSI) systems 20 (2), 371-375, 2011 | 583 | 2011 |
| ASIC implementation of modified faster carry save adder B Ramkumar, HM Kittur, PM Kannan Eur. J. Sci. Res 42 (1), 53-58, 2010 | 294 | 2010 |
| First principle simulations of various magnetic tunnel junctions $\kern-2pt $ for $\kern-2pt $ applications in magnetoresistive random access memories M Chakraverty, HM Kittur, PA Kumar IEEE Transactions on nanotechnology 12 (6), 971-977, 2013 | 58 | 2013 |
| Precharge-free, low-power content-addressable memory M Zackriya, HM Kittur IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016 | 57 | 2016 |
| A novel read scheme for large size one-resistor resistive random access memory array M Zackriya, HM Kittur, A Chin Scientific reports 7 (1), 42375, 2017 | 56 | 2017 |
| Temperature dependent resistance of magnetic tunnel junctions as a quality proof of the barrier U Rüdiger, R Calarco, U May, K Samm, J Hauch, H Kittur, M Sperlich, ... Journal of Applied Physics 89 (11), 7573-7575, 2001 | 43 | 2001 |
| Temperature-dependent magnetoresistance of magnetic tunnel junctions with ultraviolet light-assisted oxidized barriers U May, K Samm, H Kittur, J Hauch, R Calarco, U Rüdiger, G Güntherodt Applied Physics Letters 78 (14), 2026-2028, 2001 | 37 | 2001 |
| Characterization of epitaxial growth of Fe (1 1 0) on (1 1− 2 0) sapphire substrates driven by Mo (1 1 0) seed layers U May, R Calarco, JO Hauch, H Kittur, M Fonine, U Rüdiger, G Güntherodt Surface science 489 (1-3), 144-150, 2001 | 25 | 2001 |
| Design of 4 bit flash ADC using TMCC & NOR ROM encoder in 90nm CMOS technology KN Hosur, GV Attimarad, HM Kittur 2015 International Conference on Trends in Automation, Communications and …, 2015 | 18 | 2015 |
| ASIC based logarithmic multiplier using iterative pipelined architecture RK Agrawal, HM Kittur 2013 IEEE Conference on Information & Communication Technologies, 362-366, 2013 | 18 | 2013 |
| Content addressable memory—early predict and terminate precharge of match-line MV Zackriya, HM Kittur IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 385-387, 2016 | 16 | 2016 |
| 4-transistors of dynamic memristor based TCAM N Mishra, HM Kittur International Journal of Engineering Research and Applications (IJERA) 2 (3 …, 2012 | 13 | 2012 |
| Low power and efficient dadda multiplier S Ravi, GS Nair, R Narayan, HM Kittur Research Journal of Applied Sciences, Engineering and Technology 9 (1), 53-57, 2015 | 12 | 2015 |
| Area and power efficient network on chip router architecture S Sahu, HM Kittur 2013 IEEE Conference on Information & Communication Technologies, 855-859, 2013 | 12 | 2013 |
| First Principle Study of Tunnel Currents through CeO2, Y2O3, TiO2 and Al2O3 Dielectrics in MOSFETs for Ultra Large Scale Integration M Chakraverty, HM Kittur Advanced Materials Research 584, 428-432, 2012 | 12 | 2012 |
| Energy efficient low area error tolerant adder with higher accuracy R Sakthivel, HM Kittur Circuits, Systems, and Signal Processing 33, 2625-2641, 2014 | 11 | 2014 |
| Capacitance driven clock mesh synthesis to minimize skew and power dissipation J Reuben, S Nashit, HM Kittur IEICE Electronics Express 10 (24), 20130850-20130850, 2013 | 10 | 2013 |
| Low power, high speed hybrid clock divider circuit J Reuben, ZV Mohammed, HM Kittur 2013 International Conference on Circuits, Power and Computing Technologies …, 2013 | 10 | 2013 |
| Faster and energy-efficient signed multipliers B Ramkumar, HM Kittur VLSI Design 2013, 13-13, 2013 | 10 | 2013 |
| An optimized architecture to perform image compression and encryption simultaneously using modified DCT algorithm SVV Sateesh, R Sakthivel, K Nirosha, HM Kittur 2011 international conference on signal processing, communication, computing …, 2011 | 10 | 2011 |
