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Armin Belghadr
Armin Belghadr
Shahid Beheshti University, Department of Computer Science and Engineering
Verified email at sbu.ac.ir - Homepage
Title
Cited by
Cited by
Year
FIR filter realization via deferred end-around carry modular addition
A Belghadr, G Jaberipur
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (9), 2878-2888, 2018
152018
Fast division in the residue number system {2n+ 1, 2n, 2n-1} based on shortcut mixed radix conversion
Z Torabi, G Jaberipur, A Belghadr
Computers & Electrical Engineering 83, 106571, 2020
102020
Impact of diminished-1 encoding on residue number systems arithmetic units and converters
G Jaberipur, A Belghadr, S Nejati
Computers & Electrical Engineering 75, 61-76, 2019
92019
(5+ 2⌈ log n⌉) ΔG diminished-1 modulo-(2n+ 1) unified adder/subtractor with full zero handling
G Jaberipur, A Belghadr
Computers & Electrical Engineering 61, 95-103, 2017
42017
Three-dimensional physical design flow for monolithic 3D-FPGAs to improve timing closure and chip area
A Belghadr, A Jahanian
Journal of Circuits, Systems and Computers 26 (10), 1750154, 2017
32017
Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs
A Belghadr, A Jahanian
Integration 47 (1), 96-104, 2014
32014
Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set
A Belghadr, G Jaberipur
Signal, Image and Video Processing 16 (6), 1443-1454, 2022
22022
An RNS Comparator via Dynamic Range Partitioning: The Case of {2n-1, 2n, 2 n+ 1-1}
Z Torabi, A Belghadr
THE CSI JOURNAL ON COMPUTER SCIENCE AND ENGINEERING 16 (2), 38-43, 2019
22019
Fast and Power Efficient Signed/Unsigned RNS Comparator & Sign Detector
Z Torabi, A Belghadr
Journal of Electrical and Computer Engineering Innovations (JECEI) 11 (1), 41-50, 2023
2023
Low-Power CMOS/Nanomaterial Three-Dimensional Field Programmable Gate Array Architecture
H Sharifi, F Sharifi, A Belghadr
Quantum Matter 5 (4), 612-615, 2016
2016
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