| Protecting analog circuits with parameter biasing obfuscation VV Rao, I Savidis 2017 18th IEEE Latin American Test Symposium (LATS), 1-6, 2017 | 47 | 2017 |
| Mesh based obfuscation of analog circuit properties VV Rao, I Savidis 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 22 | 2019 |
| Securing analog mixed-signal integrated circuits through shared dependencies K Juretus, V Venugopal Rao, I Savidis Proceedings of the 2019 on Great Lakes Symposium on VLSI, 483-488, 2019 | 18 | 2019 |
| Parameter biasing obfuscation for analog IP protection VV Rao, I Savidis 2017 IEEE International Symposium on Hardware Oriented Security and Trust …, 2017 | 14 | 2017 |
| Performance and security analysis of parameter-obfuscated analog circuits VV Rao, I Savidis IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12 …, 2021 | 11 | 2021 |
| Security vulnerabilities of obfuscated analog circuits VV Rao, K Juretus, I Savidis 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 9 | 2020 |
| Transistor sizing for parameter obfuscation of analog circuits using satisfiability modulo theory VV Rao, I Savidis 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 102-106, 2018 | 5 | 2018 |
| Analysis of the Security Vulnerabilities of 2.5-D and 3-D Integrated Circuits VV Rao, A Sasan, I Savidis 2022 23rd International Symposium on Quality Electronic Design (ISQED), 1-7, 2022 | 4 | 2022 |
| Securing analog mixed-signal integrated circuits through shared dependencies I Savidis, VV Rao, KJ Juretus US Patent 11,270,031, 2022 | 3 | 2022 |
| Security Oriented Analog Circuit Design Using Satisfiability Modulo Theory Based Search Space Exploration V Rao, I Savidis Government Microcircuit Applications & Critical Technology Conference, 2018 | 2 | 2018 |
| Hidden Costs of Analog Deobfuscation Attacks VV Rao, K Juretus, I Savidis IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2023 | | 2023 |
| Practical Performance of Analog Attack Techniques VV Rao, K Juretus, I Savidis 2022 IEEE International Symposium on Hardware Oriented Security and Trust …, 2022 | | 2022 |
| Transistor sizing for parameter obfuscation of analog circuits VV Rao, I Savidis US Patent 11,157,674, 2021 | | 2021 |
| Protecting analog circuits with parameter biasing obfuscation I Savidis, VV Rao, K Juretus US Patent 10,923,442, 2021 | | 2021 |
| Multi-Objective Simulation-based Optimization of Analog Transistor Sizing VV Rao, I Savidis Proceedings of the Government Microcircuit Applications and Critical …, 2020 | | 2020 |
