Reetuparna Das
Reetuparna Das
Verified email at umich.edu
Title
Cited by
Cited by
Year
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
J Kim, C Nicopoulos, D Park, R Das, Y Xie, V Narayanan, MS Yousif, ...
Proceedings of the 34th annual international symposium on Computer …, 2007
3282007
MIRA: A multi-layered on-chip interconnect router architecture
D Park, S Eachempati, R Das, AK Mishra, Y Xie, N Vijaykrishnan, CR Das
2008 International Symposium on Computer Architecture, 251-261, 2008
2742008
Aérgia: exploiting packet latency slack in on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
ACM SIGARCH computer architecture news 38 (3), 106-116, 2010
2232010
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
R Das, S Eachempati, AK Mishra, V Narayanan, CR Das
2009 IEEE 15th International Symposium on High Performance Computer …, 2009
2232009
Application-aware prioritization mechanisms for on-chip networks
R Das, O Mutlu, T Moscibroda, CR Das
2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009
2202009
Scalpel: Customizing dnn pruning to the underlying hardware parallelism
J Yu, A Lukefahr, D Palframan, G Dasika, R Das, S Mahlke
ACM SIGARCH Computer Architecture News 45 (2), 548-560, 2017
2022017
Composite cores: Pushing heterogeneity into a core
A Lukefahr, S Padmanabha, R Das, FM Sleiman, R Dreslinski, ...
2012 45th Annual IEEE/ACM international symposium on microarchitecture, 317-328, 2012
1842012
Catnap: Energy proportional multiple network-on-chip
R Das, S Narayanasamy, SK Satpathy, RG Dreslinski
ACM SIGARCH Computer Architecture News 41 (3), 320-331, 2013
1522013
A case for dynamic frequency tuning in on-chip networks
AK Mishra, R Das, S Eachempati, R Iyer, N Vijaykrishnan, CR Das
2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture …, 2009
1292009
Compute caches
S Aga, S Jeloka, A Subramaniyan, S Narayanasamy, D Blaauw, R Das
2017 IEEE International Symposium on High Performance Computer Architecture …, 2017
1112017
Application-to-core mapping policies to reduce memory system interference in multi-core systems
R Das, R Ausavarungnirun, O Mutlu, A Kumar, M Azimi
2013 IEEE 19th International Symposium on High Performance Computer …, 2013
1112013
Performance and power optimization through data compression in network-on-chip architectures
R Das, AK Mishra, C Nicopoulos, D Park, V Narayanan, R Iyer, MS Yousif, ...
2008 IEEE 14th International Symposium on High Performance Computer …, 2008
1062008
Neural cache: Bit-serial in-cache acceleration of deep neural networks
C Eckert, X Wang, J Wang, A Subramaniyan, R Iyer, D Sylvester, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
1012018
Power-aware NoCs through routing and topology reconfiguration
R Parikh, R Das, V Bertacco
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
852014
ANVIL: Software-based protection against next-generation rowhammer attacks
ZB Aweke, SF Yitbarek, R Qiao, R Das, M Hicks, Y Oren, T Austin
ACM SIGPLAN Notices 51 (4), 743-755, 2016
842016
Swizzle-switch networks for many-core systems
K Sewell, RG Dreslinski, T Manville, S Satpathy, N Pinckney, G Blake, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (2 …, 2012
712012
Design of a dynamic priority-based fast path architecture for on-chip interconnects
D Park, R Das, C Nicopoulos, J Kim, N Vijaykrishnan, R Iyer, CR Das
15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007), 15-20, 2007
592007
Trace based phase prediction for tightly-coupled heterogeneous cores
S Padmanabha, A Lukefahr, R Das, S Mahlke
2013 46th Annual IEEE/ACM International Symposium on Microarchitecture …, 2013
572013
In-memory data parallel processor
D Fujiki, S Mahlke, R Das
ACM SIGPLAN Notices 53 (2), 1-14, 2018
462018
Scaling towards kilo-core processors with asymmetric high-radix topologies.
N Abeyratne, R Das, Q Li, K Sewell, B Giridhar, RG Dreslinski, DT Blaauw, ...
HPCA, 496-507, 2013
462013
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Articles 1–20