Ali Jahanian

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Morteza Saheb ZamaniProfessor, Amirkabir University of TechnologyVerified email at aut.ac.ir
Sharareh ZamanzadehShahid Beheshti universityVerified email at sbu.ac.ir
Ghassem JaberipurProfessor for the Brain Pool Program in Chosun University, Gwangju, South Korea, SBU retiredVerified email at sbu.ac.ir
Abdoreza PishvaieAssistant Professor, KIAU, Karaj, IranVerified email at kiau.ac.ir
maryam taajobianDepartment of Computer Engineering, Mahdishahr Branch, Islamic Azad University, Mahdishahr, IRANVerified email at iau.ac.ir
Mercedeh SanjabiPHD in computer architecture, shahid beheshti universityVerified email at sbu.ac.ir
Mehdi SaeediPrincipal Staff (AMD)Verified email at amd.com
Alireza AbdoliResearcher in University of California, RiversideVerified email at ucr.edu
Saba AmanollahiPhDVerified email at sbu.ac.ir
Hamed HosseintalaeeShahid Beheshti UniversityVerified email at sbu.ac.ir
Shadi MomtahenPostdoctoral Research Fellow in Medicine at ICORD, University of British Columbia (UBC)Verified email at sfu.ca
Vahhab Samadi BokharaiePhD Student, Shahid Beheshti UniversityVerified email at sbu.ac.ir
Sirvan KhalighiEmory UniversityVerified email at emory.edu
Adel DokhanchiArizona State UniversityVerified email at asu.edu
somayeh maabiPHD candidate in computer architecture, Shahid Beheshti UniversityVerified email at sbu.ac.ir
Armin BelghadrShahid Beheshti University, Department of Computer Science and EngineeringVerified email at sbu.ac.ir
Hamid SafizadehUniversity of MinnesotaVerified email at umn.edu
Mohsen NaderiFinancial Computing and Analytics Group, Department of Computer Science, UCLVerified email at cs.ucl.ac.uk
Bahman JavadiFull Professor, Western Sydney UniversityVerified email at uws.edu.au
Mohammadkazem Akbari FatidehiProfessor of CE & IT Dept., Amirkabir University of TechnologyVerified email at aut.ac.ir

Ali Jahanian

Associate Professor at Shahid Beheshti University

Verified email at sbu.ac.ir - Homepage

Hardware Security Biochip Design DNA Computing


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Improved CMOS (4; 2) compressor designs for parallel multipliers A Pishvaie, G Jaberipur, A Jahanian Computers & Electrical Engineering 38 (6), 1703-1716, 2012	56	2012
High-performance CMOS (4: 2) compressors A Pishvaie, G Jaberipur, A Jahanian International journal of electronics 101 (11), 1511-1525, 2014	36	2014
Prediction and reduction of routing congestion M Saeedi, MS Zamani, A Jahanian Proceedings of the 2006 international symposium on Physical design, 72-77, 2006	31	2006
Redesigned CMOS (4; 2) compressor for fast binary multipliers A Pishvaie, G Jaberipur, A Jahanian Canadian Journal of Electrical and Computer Engineering 36 (3), 111-115, 2013	26	2013
A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform H Daryanavard, M Eshghi, A Jahanian The Journal of Supercomputing 71, 121-143, 2015	13	2015
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering S Zamanzadeh, A Jahanian 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013	12	2013
Area efficient, low power and robust design for add-compare-select units MK Akbari, AH Jahanian, M Naderi, B Javadi Euromicro Symposium on Digital System Design, 2004. DSD 2004., 611-614, 2004	12	2004
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology S Zamanzadeh, A Jahanian Microprocessors and Microsystems 42, 1-9, 2016	10	2016
A general-purpose field-programmable pin-constrained digital microfluidic biochip A Abdoli, A Jahanian 2015 18th CSI International Symposium on Computer Architecture and Digital …, 2015	10	2015
Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process V Samadi Bokharaie, A Jahanian The Journal of Supercomputing, 1-26, 2022	9	2022
Improved Line Tracking System for Autonomous Navigation of High-Speed Vehicle YZ Khafri, A Jahanian IAES International Journal of Robotics and Automation 1 (3), 163, 2012	9	2012
EduCAD: An efficient, flexible and easily revisable physical design tool for educational purposes S Amanollahi, A Jahanian design, automation and test in Europe university booth (DATE), 130-131, 2011	9	2011
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network N MohammadZadeh, M Mirsaeedi, A Jahanian, MS Zamani 2009 Design, Automation & Test in Europe Conference & Exhibition, 833-838, 2009	9	2009
Layout vulnerability reduction against trojan insertion using security-aware white space distribution H Hossein-Talaee, A Jahanian 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 551-555, 2017	8	2017
DENA: A configurable microarchitecture and design flow for biomedical DNA-based logic design Z Beiki, A Jahanian IEEE transactions on biomedical circuits and systems 11 (5), 1077-1086, 2017	8	2017
Higher Flexibililty of Recon gurable Digital Micro/Nano Fluidic Biochips using an FPGA-Inspired Architecture M Taajobian, A Jahanian Scientia Iranica 23 (3), 1554-1562, 2016	8	2016
ParSA: parallel simulated annealing placement algorithm for multi-core systems M Sanjabi, A Jahanian, S Amanollahi, N Miralaei The 16th CSI International Symposium on Computer Architecture and Digital …, 2012	8	2012
Side-channel leakage assessment metrics and methodologies at design cycle: a case study for a cryptosystem VS Bokharaie, A Jahanian Journal of Information Security and Applications 54, 102561, 2020	7	2020
Multi‐threshold and multi‐input DNA logic design style for profiling the microRNA biomarkers of real cancers M Sanjabi, A Jahanian IET nanobiotechnology 13 (7), 665-673, 2019	7	2019
Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips A Abdoli, A Jahanian 2015 CSI symposium on real-time and embedded systems and technologies (RTEST …, 2015	7	2015

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