| Hardware implementation of a novel adaptive version of Deflate compression algorithm M Tahghighi, M Mousavi, P Khadivi 2010 18th Iranian Conference on Electrical Engineering, 566-569, 2010 | 22 | 2010 |
| A generic methodology to compute design sensitivity to SEU in SRAM-based FPGA M Mousavi, HR Pourshaghaghi, M Tahghighi, R Jordans, H Corporaal 2018 21st Euromicro Conference on Digital System Design (DSD), 221-228, 2018 | 18 | 2018 |
| Analytical delay model for CPU-FPGA data paths in programmable system-on-chip FPGA M Tahghighi, S Sinha, W Zhang Applied Reconfigurable Computing: 12th International Symposium, ARC 2016 …, 2016 | 6 | 2016 |
| A new hybrid topology for network on chip M Tahghighi, M Mousavi, P Khadivi, K Bazargan 20th Iranian Conference on Electrical Engineering (ICEE2012), 769-774, 2012 | 4 | 2012 |
| Accelerate pattern recognition for cyber security analysis M Tahghighi, W Zhang Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019 | | 2019 |
| Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing M Tahghighi, W Zhang, S Sinha 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 667-672, 2016 | | 2016 |
| Using CPU/FPGA heterogeneous architectures for implicitly defined complex event detection M Tahghighi | | 2016 |
| Using randomization to cope with circuit uncertainty H Safizadeh, M Tahghighi, EK Ardestani, G Tavasoli, K Bazargan 2009 Design, Automation & Test in Europe Conference & Exhibition, 815-820, 2009 | | 2009 |
Pejman KhadiviSeattle University, Virginia Tech, Isfahan University of TechnologyVerified email at seattleu.edu
