Reza Hojabr
Cited by
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Skippynn: An embedded stochastic-computing accelerator for convolutional neural networks
R Hojabr, K Givaki, SMR Tayaranian, P Esfahanian, A Khonsari, ...
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019
Power-efficient accelerator design for neural networks using computation reuse
A Yasoubi, R Hojabr, M Modarressi
IEEE computer architecture letters 16 (1), 72-75, 2016
Customizing clos network-on-chip for neural networks
R Hojabr, M Modarressi, M Daneshtalab, A Yasoubi, A Khonsari
IEEE Transactions on Computers 66 (11), 1865-1877, 2017
μir-an intermediate representation for transforming and optimizing the microarchitecture of application accelerators
A Sharifian, R Hojabr, N Rahimi, S Liu, A Guha, T Nowatzki, A Shriraman
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
On the resilience of deep learning for reduced-voltage FPGAs
K Givaki, B Salami, R Hojabr, SMR Tayaranian, A Khonsari, D Rahmati, ...
2020 28th Euromicro International Conference on Parallel, Distributed and …, 2020
SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs
R Hojabr, A Sedaghati, A Sharifian, A Khonsari, A Shriraman
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
CuPAN–high throughput on-chip interconnection for neural networks
A Yasoubi, R Hojabr, H Takshi, M Modarressi, M Daneshtalab
International Conference on Neural Information Processing, 559-566, 2015
Using residue number systems to accelerate deterministic bit-stream multiplication
K Givaki, R Hojabr, MH Najafi, A Khonsari, MH Gholamrezayi, S Gorgin, ...
2019 IEEE 30th International Conference on Application-specific Systems …, 2019
Real-Time Formal Verification of Autonomous Systems With An FPGA
M Bui, M Lu, R Hojabr, M Chen, A Shriraman
arXiv preprint arXiv:2012.04011, 2020
Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA
M Bui, M Lu, R Hojabr, M Chen, A Shriraman
2021 IEEE/RSJ International Conference on Intelligent Robots and Systems …, 2021
X-cache: a modular architecture for domain-specific caches
A Sedaghati, M Hakimi, R Hojabr, A Shriraman
Proceedings of the 49th Annual International Symposium on Computer …, 2022
X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions
N Vedula, R Hojabr, A Khonsari, A Shriraman
2021 30th International Conference on Parallel Architectures and Compilation …, 2021
High Performance Interconnection Networks for Neural Network Accelerators
R Hojabr
School of ECE, University of Tehran, 2021
High-Performance Deterministic Stochastic Computing Using Residue Number System
K Givaki, R Hojabr, MH Gholamrezaei, A Khonsari, S Gorgin, D Rahmati, ...
IEEE Design & Test 38 (6), 60-68, 2021
TaxoNN: a Light-Weight Accelerator for Deep Neural Network Training
R Hojabr, K Givaki, K Pourahmadi, P Nooralinejad, A Khonsari, ...
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020
Feedforward neural networks on massively parallel architectures
R Hojabr, A Khonsari, M Modarressi, M Daneshtalab
Hardware Architectures for Deep Learning, 53, 2020
2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT)| 978-1-6654-4278-7/21/$31.00© 2021 IEEE| DOI: 10.1109/PACT52795. 2021.00033
B Akin, C Angermueller, D Baek, W Baek, CR Banbury, Y Bao, A Basu, ...
2017 Index IEEE Computer Architecture Letters Vol. 16
N Abu-Ghazaleh, A Adileh, A Agrawal, H Ahmadvand, JH Ahn, ...
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