| A top-down method for performance analysis and counters architecture A Yasin 2014 IEEE International Symposium on Performance Analysis of Systems and …, 2014 | 386 | 2014 |
| Inside 6th-generation intel core: New microarchitecture code-named skylake J Doweck, WF Kao, AK Lu, J Mandelblat, A Rahatekar, L Rappoport, ... IEEE Micro 37 (2), 52-62, 2017 | 216 | 2017 |
| Deep-dive analysis of the data analytics workload in cloudsuite A Yasin, Y Ben-Asher, A Mendelson 2014 IEEE international symposium on workload characterization (IISWC), 202-211, 2014 | 76 | 2014 |
| Fine-grain power breakdown of modern out-of-order cores and its implications on skylake-based systems J Haj-Yihia, A Yasin, YB Asher, A Mendelson ACM Transactions on Architecture and Code Optimization (TACO) 13 (4), 1-25, 2016 | 58 | 2016 |
| Intel alder lake cpu architectures E Rotem, A Yoaz, L Rappoport, SJ Robinson, JY Mandelblat, A Gihon, ... IEEE Micro 42 (3), 13-19, 2022 | 37 | 2022 |
| Establishing a base of trust with performance counters for enterprise workloads A Nowak, A Yasin, A Mendelson, W Zwaenepoel 2015 USENIX Annual Technical Conference (USENIX ATC 15), 541-548, 2015 | 34 | 2015 |
| Technologies for managing the efficiency of workload execution JG Van De Groenendaal, M Ganguli, A Yasin US Patent 10,687,127, 2020 | 25 | 2020 |
| Virtualizing precise event based sampling MC Merten, BC Strong, MW Chynoweth, GG Zhou, A Kleen, KC Weier, ... US Patent 9,965,375, 2018 | 24 | 2018 |
| A metric-guided method for discovering impactful features and architectural insights for skylake-based processors A Yasin, J Haj-Yahya, Y Ben-Asher, A Mendelson ACM Transactions on Architecture and Code Optimization (TACO) 16 (4), 1-25, 2019 | 22 | 2019 |
| Compiler-directed power management for superscalars J Haj-Yihia, YB Asher, E Rotem, A Yasin, R Ginosar ACM Transactions on Architecture and Code Optimization (TACO) 11 (4), 1-21, 2015 | 17 | 2015 |
| A methodology for OLTP micro-architectural analysis U Sirin, A Yasin, A Ailamaki Proceedings of the 13th International Workshop on Data Management on New …, 2017 | 15 | 2017 |
| Inside 6th gen Intel®Core™: New microarchitecture code named skylake I Anati, D Blythe, J Doweck, H Jiang, W Kao, J Mandelblat, L Rappoport, ... 2016 IEEE Hot Chips 28 Symposium (HCS), 1-39, 2016 | 14 | 2016 |
| Method and apparatus for processor performance monitoring MW Chynoweth, JD Combs, AD Schmid, KC Weier, A Yasin, JW Brandt, ... US Patent 9,465,680, 2016 | 11 | 2016 |
| Processor operating by selecting smaller of requested frequency and an energy performance gain (EPG) frequency Y Aizik, E Weissmann, E Rotem, Y Sabin, D Rajwan, A Yasin US Patent 9,671,853, 2017 | 9 | 2017 |
| DOEE: Dynamic optimization framework for better energy efficiency J Haj-Yihia, A Yasin, Y Ben-Asher Proceedings of the Symposium on High Performance Computing, 107-114, 2015 | 9 | 2015 |
| How to tune applications using a top-down characterization of microarchitectural issues J Marusarz, S Cepeda, A Yasin Technical report, 2013 | 8 | 2013 |
| Causing an interrupt based on event count A Yasin, PJ Irelan, O Levy, E Ziedan, G Zhou US Patent 9,575,766, 2017 | 7 | 2017 |
| Instruction and logic for adaptive event-based sampling A Yasin, PJ Irelan, GG Zhou US Patent App. 14/332,736, 2016 | 7 | 2016 |
| Micro-architectural analysis of in-memory OLTP: Revisited U Sirin, P Tözün, D Porobic, A Yasin, A Ailamaki The VLDB Journal 30, 641-665, 2021 | 6 | 2021 |
| Tuning performance via metrics with expectations A Yasin, A Mendelson, Y Ben-Asher IEEE Computer Architecture Letters 18 (2), 91-94, 2019 | 6 | 2019 |
Yosi Ben AsherProfessor of Computer Science, University of HaifaVerified email at cs.haifa.ac.il
