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Yan Zhu
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A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Journal of Solid-State Circuits 45 (6), 1111-1121, 2010
6892010
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash
Y Zhu, CH Chan, SW Sin, F Maloberti, RP Martins
IEEE Computer Society, 2013
196*2013
A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS
CH Chan, Y Zhu, UF Chio, SW Sin, U Seng-Pan, RP Martins
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian, 233-236, 2011
832011
Split-SAR ADCs: Improved linearity with power and speed optimization
Y Zhu, CH Chan, UF Chio, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE transactions on very large scale integration (VLSI) systems 22 (2), 372-383, 2014
812014
A 3.8 mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
VLSI Circuits (VLSIC), 2012 Symposium on, 86-87, 2012
732012
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
CH Chan, Y Zhu, WH Zhang, U Seng-Pan, RP Martins
IEEE Journal of Solid-State Circuits 53 (3), 850-860, 2018
652018
A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC
SS Wong, UF Chio, Y Zhu, SW Sin, U Seng-Pan, RP Martins
IEEE journal of solid-state circuits 48 (8), 1783-1794, 2013
652013
3.5 A 0.6 V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
M Zhang, CH Chan, Y Zhu, RP Martins
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 66-68, 2019
64*2019
26.5 A 5.5 mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins
Solid-State Circuits Conference-(ISSCC), 2015 IEEE International, 1-3, 2015
612015
Design and experimental verification of a power effective flash-SAR subranging ADC
UF Chio, HG Wei, Y Zhu, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (8), 607-611, 2010
562010
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier
W Jiang, Y Zhu, M Zhang, CH Chan, RP Martins
IEEE Journal of Solid-State Circuits, 2019
492019
60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration
CH Chan, Y Zhu, C Li, WH Zhang, IM Ho, L Wei, U Seng-Pan, RP Martins
IEEE Journal of Solid-State Circuits, 2017
462017
A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC
CH Chan, Y Zhu, SW Sin, RP Martins
IEEE Journal of Solid-State Circuits 51 (2), 365-377, 2016
442016
3.2 A 7.6 mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
W Jiang, Y Zhu, M Zhang, CH Chan, RP Martins
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 60-62, 2019
422019
A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC
CH Chan, Y Zhu, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Transactions on Circuits and Systems I: Regular Papers, 2017
402017
An 11b 450 MS/s three-way time-interleaved subranging pipelined-SAR ADC in 65 nm CMOS
Y Zhu, CH Chan, U Seng-Pan, RP Martins
IEEE Journal of Solid-State Circuits 51 (5), 1223-1234, 2016
402016
A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC
Y Zhu, CH Chan, SW Sin, U Seng-Pan, RP Martins
VLSI Circuits (VLSIC), 2012 Symposium on, 90-91, 2012
402012
Linearity analysis on a series-split capacitor array for high-speed SAR ADCs
Y Zhu, U Chio, HG Wei, SW Sin, RP Martins
VLSI Design 2010, 14, 2010
402010
A 50-fJ 10-b 160-MS/s pipelined-SAR ADC decoupled flip-around MDAC and self-embedded offset cancellation
Y Zhu, CH Chan, SW Sin, U Seng-Pan, RP Martins, F Maloberti
IEEE Journal of Solid-State Circuits 47 (11), 2614-2626, 2012
382012
A power-efficient capacitor structure for high-speed charge recycling SAR ADCs
Y Zhu, UF Chio, HG Wei, SW Sin, U Seng-Pan, RP Martins
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International …, 2008
382008
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