Arish Satheesan
Title
Cited by
Cited by
Year
An efficient binary multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
S Arish, RK Sharma
IEEE - Communication Technologies (GCCT), 2015 Global Conference on, 192-196, 2015
142015
An efficient floating point multiplier design for high speed applications using Karatsuba algorithm and Urdhva-Tiryagbhyam algorithm
S Arish, RK Sharma
IEEE - 2015 International Conference on Signal Processing and Communication …, 2015
14*2015
Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
S Arish, RK Sharma
IEEE - Signal Processing and Integrated Networks (SPIN), 2015 2nd …, 2015
122015
Run-Time-Reconfigurable Multi-Precision Floating-Point Matrix Multiplier Intellectual Property Core on FPGA
S Arish, RK Sharma
Springer US (CSSP) - International Journal of Circuits, Systems, and Signal …, 2017
52017
Optimization of Convolutional Neural Networks on Resource Constrained Devices
S Arish, S Sharad, KG Smitha
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019
22019
Low-Rate Overuse Flow Tracer (LOFT): An Efficient and Scalable Algorithm for Detecting Overuse Flows
S Scherrer, CY Wu, YH Chiang, B Rothenberger, DE Asoni, A Sateesan, ...
arXiv preprint arXiv:2102.01397, 2021
2021
Novel Bloom filter algorithms and architectures for ultra-high-speed network security applications
A Sateesan, J Vliegen, J Daemen, N Mentens
Euromicro DSD 2020, 2020
2020
DASH: Design Automation for Synthesis and Hardware Generation for CNN
A Sateesan, S Sinha, KG Smitha
2020 International Conference on Field-Programmable Technology (ICFPT), 2020
2020
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