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Debapriya Basu Roy
Debapriya Basu Roy
Assistant Professor, IIT Kanpur
Verified email at cse.iitk.ac.in
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Masked accelerators and instruction set extensions for post-quantum cryptography
T Fritzmann, M Van Beirendonck, D Basu Roy, P Karl, T Schamberger, ...
IACR Transactions on Cryptographic Hardware and Embedded Systems 2022 (1 …, 2021
762021
Role of power grid in side channel attack and power-grid-aware secure design
X Wang, W Yueh, DB Roy, S Narasimhan, Y Zheng, S Mukhopadhyay, ...
Proceedings of the 50th Annual Design Automation Conference, 1-9, 2013
572013
High-speed implementation of ECC scalar multiplication in GF (p) for generic Montgomery curves
DB Roy, D Mukhopadhyay
IEEE transactions on very large scale integration (VLSI) systems 27 (7 …, 2019
512019
Number “Not Used” Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates
P Ravi, DB Roy, S Bhasin, A Chattopadhyay, D Mukhopadhyay
Constructive Side-Channel Analysis and Secure Design: 10th International …, 2019
492019
Fault template attacks on block ciphers exploiting fault propagation
S Saha, A Bag, D Basu Roy, S Patranabis, D Mukhopadhyay
Advances in Cryptology–EUROCRYPT 2020: 39th Annual International Conference …, 2020
432020
A framework to counter statistical ineffective fault analysis of block ciphers using domain transformation and error correction
S Saha, D Jap, DB Roy, A Chakraborty, S Bhasin, D Mukhopadhyay
IEEE Transactions on Information Forensics and Security 15, 1905-1919, 2019
342019
Tile before multiplication: An efficient strategy to optimize DSP multiplier for accelerating prime field ECC for NIST curves
DB Roy, D Mukhopadhyay, M Izumi, J Takahashi
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
332014
ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF(p)
DB Roy, P Das, D Mukhopadhyay
International Conference on Selected Areas in Cryptography, 161-177, 2015
322015
Lightweight design-for-security strategies for combined countermeasures against side channel and fault analysis in IoT applications
S Patranabis, DB Roy, A Chakraborty, N Nagar, A Singh, ...
Journal of Hardware and Systems Security 3, 103-131, 2019
292019
CC meets FIPS: A hybrid test methodology for first order side channel analysis
DB Roy, S Bhasin, S Guilley, A Heuser, S Patranabis, D Mukhopadhyay
IEEE Transactions on Computers 68 (3), 347-361, 2018
272018
From theory to practice of private circuit: A cautionary note
DB Roy, S Bhasin, S Guilley, JL Danger, D Mukhopadhyay
2015 33rd IEEE International Conference on Computer Design (ICCD), 296-303, 2015
262015
Integrated sensor: a backdoor for hardware Trojan insertions?
XT Ng, Z Naj, S Bhasin, DB Roy, JL Danger, S Guilley
2015 Euromicro conference on digital system design, 415-422, 2015
212015
Leak me if you can: Does tvla reveal success rate?
DB Roy, S Bhasin, S Guilley, A Heuser, S Patranabis, D Mukhopadhyay
Cryptology ePrint Archive, 2016
182016
Efficient hardware/software co-design for post-quantum crypto algorithm SIKE on ARM and RISC-V based microcontrollers
DB Roy, T Fritzmann, G Sigl
Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020
162020
Post quantum ecc on fpga platform
DB Roy, D Mukhopadhyay
Cryptology ePrint Archive, 2019
152019
Using Tweaks To Design Fault Resistant Ciphers (Full Version)
S Patranabis, DB Roy, D Mukhopadhyay
Proceedings of the Computing Frontiers Conference, 402-408, 2017
142017
Shuffling across rounds: A lightweight strategy to counter side-channel attacks
S Patranabis, DB Roy, PK Vadnala, D Mukhopadhyay, S Ghosh
2016 IEEE 34th International Conference on Computer Design (ICCD), 440-443, 2016
142016
Count your toggles: A new leakage model for pre-silicon power analysis of crypto designs
R Sadhukhan, P Mathew, DB Roy, D Mukhopadhyay
Journal of Electronic Testing 35, 605-619, 2019
132019
Combining puf with rluts: a two-party pay-per-device ip licensing scheme on fpgas
DB Roy, S Bhasin, I Nikolić, D Mukhopadhyay
ACM Transactions on Embedded Computing Systems (TECS) 18 (2), 1-22, 2019
122019
Reconfigurable LUT: A double edged sword for security-critical applications
DB Roy, S Bhasin, S Guilley, JL Danger, D Mukhopadhyay, XT Ngo, ...
Security, Privacy, and Applied Cryptography Engineering: 5th International …, 2015
122015
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