| On the connectivity in finite ad hoc networks M Desai, D Manjunath IEEE Communications letters 6 (10), 437-439, 2002 | 246 | 2002 |
| A characterization of the smallest eigenvalue of a graph M Desai, V Rao Journal of Graph Theory 18 (2), 181-194, 1994 | 168 | 1994 |
| The effect of high-k gate dielectrics on deep submicrometer CMOS device and circuit performance NR Mohapatra, MP Desai, SG Narendra, VR Rao IEEE transactions on electron devices 49 (5), 826-831, 2002 | 99 | 2002 |
| Sizing of clock distribution networks for high performance CPU chips MP Desai, R Cvijetic, J Jensen Proceedings of the 33rd annual Design Automation Conference, 389-394, 1996 | 89 | 1996 |
| Modeling of parasitic capacitances in deep submicrometer conventional and high-K dielectric MOS transistors NR Mohapatra, MP Desai, SG Narendra, VR Rao IEEE Transactions on Electron Devices 50 (4), 959-966, 2003 | 83 | 2003 |
| Variance reduction in Monte Carlo capacitance extraction SH Batterywala, MP Desai 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 36 | 2005 |
| The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance K Narasimhulu, MP Desai, SG Narendra, VR Rao IEEE transactions on electron devices 51 (9), 1416-1423, 2004 | 36 | 2004 |
| Decomposition of finite state machines for area, delay minimization RS Shelar, MP Desai, H Narayanan Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999 | 30 | 1999 |
| A state assignment scheme targeting performance and area BNVM Gupta, H Narayanan, MP Desai Proceedings Twelfth International Conference on VLSI Design.(Cat. No …, 1999 | 29 | 1999 |
| On the convergence of block relaxation methods for circuit simulation MP Desai, IN Hajj IEEE transactions on circuits and systems 36 (7), 948-958, 1989 | 29 | 1989 |
| The {Click2NetFPGA} Toolchain T Rinta-Aho, M Karlstedt, MP Desai 2012 USENIX Annual Technical Conference (USENIX ATC 12), 77-88, 2012 | 28 | 2012 |
| Impact of technology scaling on metastability performance of CMOS synchronizing latches MS Baghini, MP Desai Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design …, 2002 | 24 | 2002 |
| Reconfigurable finite-state machine based IP lookup engine for high-speed router M Desai, R Gupta, A Karandikar, K Saxena, V Samant IEEE Journal on Selected Areas in Communications 21 (4), 501-512, 2003 | 23 | 2003 |
| A systematic technique for verifying critical path delays in a 300MHz Alpha CPU design using circuit simulation MP Desai Proceedings of the 33rd annual Design Automation Conference, 125-130, 1996 | 23 | 1996 |
| Orthogonal partitioning and gated clock architecture for low power realization of FSMs RS Shelar, H Narayanan, MP Desai Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No …, 2000 | 22 | 2000 |
| On the convergence of reversible Markov chains MP Desai, VB Rao SIAM journal on matrix analysis and applications 14 (4), 950-966, 1993 | 21 | 1993 |
| Method and apparatus for estimating parasitic capacitance SH Batterywala, N Shenoy, M Desai US Patent 7,260,797, 2007 | 19 | 2007 |
| Silicon film thickness considerations in SOI-DTMOS P Sivaram, B Anand, MP Desai IEEE Electron Device Letters 23 (5), 276-278, 2002 | 18 | 2002 |
| Interconnect delay minimization using a novel pre-mid-post buffer strategy V Prasad, MP Desai 16th International Conference on VLSI Design, 2003. Proceedings., 417-422, 2003 | 17 | 2003 |
| A low-latency, low-power FPGA implementation of ECG signal characterization using hermite polynomials MP Desai, G Caffarena, R Jevtic, DG Márquez, A Otero Electronics 10 (19), 2324, 2021 | 16 | 2021 |
