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Weng Hong Teh
Weng Hong Teh
Unknown affiliation
Verified email at alum.mit.edu
Title
Cited by
Cited by
Year
Effect of low numerical-aperture femtosecond two-photon absorption on (SU-8) resist for ultrahigh-aspect-ratio microstereolithography
WH Teh, U Dürig, U Drechsler, CG Smith, HJ Güntherodt
Journal of applied physics 97 (5), 2005
2012005
SU-8 for real three-dimensional subdiffraction-limit two-photon microfabrication
WH Teh, U Dürig, G Salis, R Harbers, U Drechsler, RF Mahrt, CG Smith, ...
Applied physics letters 84 (20), 4095-4097, 2004
1432004
High density substrate routing in BBUL package
WH Teh, CP Chiu
US Patent 9,190,380, 2015
902015
Cross-linked PMMA as a low-dimensional dielectric sacrificial layer
WH Teh, CT Liang, M Graham, CG Smith
Journal of Microelectromechanical Systems 12 (5), 641-648, 2003
792003
Study of microstructure and resistivity evolution for electroplated copper films at near-room temperature
WH Teh, LT Koh, SM Chen, J Xie, CY Li, PD Foo
Microelectronics Journal 32 (7), 579-585, 2001
792001
Bumpless build-up layer package including an integrated heat spreader
WH Teh, D Kulkarni, CP Chiu, T Harirchian, JS Guzek
US Patent 8,912,670, 2014
472014
Near-zero curvature fabrication of miniaturized micromechanical Ni switches using electron beam cross-linked PMMA
WH Teh, JK Luo, MR Graham, A Pavlov, CG Smith
Journal of Micromechanics and Microengineering 13 (5), 591, 2003
402003
Packaged semiconductor die with bumpless die-package interface for bumpless build-up layer (BBUL) packages
P Malatkar, WH Teh, JS Guzek, RL Sankman
US Patent 9,224,674, 2015
372015
High density substrate routing in BBUL package
WH Teh, CP Chiu
US Patent 9,171,816, 2015
362015
Bumpless build-up layer package including an integrated heat spreader
WH Teh, D Kulkarni, CP Chiu, T Harirchian, JS Guzek
US Patent 9,153,552, 2015
312015
Multi-strata stealth dicing before grinding for singulation-defects elimination and die strength enhancement: experiment and simulation
WH Teh, DS Boning, RE Welsch
IEEE Transactions on Semiconductor Manufacturing 28 (3), 408-423, 2015
302015
Semiconductor package with mechanical fuse
WH Teh, KL Lin, F Eid, Q Ma
US Patent 8,633,551, 2014
302014
High density substrate routing in BBUL package
WH Teh, CP Chiu
US Patent 9,437,569, 2016
292016
Bumpless die-package interface for bumpless build-up layer (BBUL)
WH Teh, JS Guzek, RL Sankman
US Patent 9,576,909, 2017
282017
Embedded structures for package-on-package architecture
WH Teh, V Raghunathan
US Patent 8,866,287, 2014
282014
Method to inhibit metal-to-metal stiction issues in mems fabrication
WH Teh, ZM Zhao, DR Singh
US Patent App. 13/539,444, 2014
272014
Secondary device integration into coreless microelectronic device packages
WH Teh, JS Guzek
US Patent 8,937,382, 2015
26*2015
Multi die package having a die and a spacer layer in a recess
WH Teh, JS Guzek, S Zhong
US Patent 9,490,196, 2016
232016
Backside infrared interferometric patterned wafer thickness sensing for through-silicon-via (TSV) etch metrology
WH Teh, D Marx, D Grant, R Dudley
IEEE transactions on semiconductor manufacturing 23 (3), 419-422, 2010
232010
Fabrication of quasi-three-dimensional micro/nanomechanical components using electron beam cross-linked poly (methyl methacrylate) resist
WH Teh, CG Smith
Journal of Vacuum Science & Technology B: Microelectronics and Nanometer …, 2003
232003
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Articles 1–20