Bernhard Jungk
Bernhard Jungk
Albstadt-Sigmaringen University
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Area-efficient FPGA implementations of the SHA-3 finalists
B Jungk, J Apfelbeck
2011 International Conference on Reconfigurable Computing and FPGAs, 235-241, 2011
Xmss and embedded systems: Xmss hardware accelerators for risc-v
W Wang, B Jungk, J Wälde, S Deng, N Gupta, J Szefer, R Niederhagen
International Conference on Selected Areas in Cryptography, 523-550, 2019
Parameterized hardware accelerators for lattice-based cryptography and their application to the HW/SW co-design of qTESLA
W Wang, S Tian, B Jungk, N Bindel, P Longa, J Szefer
IACR transactions on cryptographic hardware and embedded systems 2020 (3), 2020
Evaluation of compact FPGA implementations for all SHA-3 finalists
B Jungk
The Third SHA-3 Candidate Conference, 2012
Among slow dwarfs and fast giants: A systematic design space exploration of KECCAK
B Jungk, M Stöttinger
2013 8th International Workshop on Reconfigurable and Communication-Centric …, 2013
A systematic study of lightweight hash functions on FPGAs
B Jungk, LR Lima, M Hiller
2014 International Conference on ReConFigurable Computing and FPGAs …, 2014
Efficient side-channel protections of ARX ciphers
B Jungk, R Petri, M Stöttinger
Cryptology ePrint Archive, 2018
On FPGA-based implementations of Gr\{o} stl
B Jungk, S Reith
Cryptology ePrint Archive, 2010
On optimized FPGA implementations of the SHA-3 Candidate Grøstl
B Jungk, S Reith, J Apfelbeck
Cryptology EPrint Archive, 2009
ASIC accelerator in 28 nm for the post-quantum digital signature scheme XMSS
P Mohan, W Wang, B Jungk, R Niederhagen, J Szefer, K Mai
2020 IEEE 38th International Conference on Computer Design (ICCD), 656-662, 2020
Serialized lightweight SHA-3 FPGA implementations
B Jungk, M Stöttinger
Microprocessors and Microsystems 71, 102857, 2019
Compact implementations of Grøstl, JH and Skein for FPGAs
B Jungk
proceedings of the ECRYPT II Hash Workshop, 2011
On comparing side-channel properties of AES and ChaCha20 on microcontrollers
Z Najm, D Jap, B Jungk, S Picek, S Bhasin
2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 552-555, 2018
Side-channel resistant AES architecture utilizing randomized composite field representations
B Jungk, M Stöttinger, J Gampe, S Reith, SA Huss
2012 International Conference on Field-Programmable Technology, 125-128, 2012
Don't fall into a trap: Physical side-channel analysis of ChaCha20-Poly1305
B Jungk, S Bhasin
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Hobbit—Smaller but faster than a dwarf: Revisiting lightweight SHA-3 FPGA implementations
B Jungk, M Stöttinger
2016 International Conference on ReConFigurable Computing and FPGAs …, 2016
Feature selection methods for non-profiled side-channel attacks on ecc
P Ravi, B Jungk, D Jap, Z Najm, S Bhasin
2018 IEEE 23rd International Conference on Digital Signal Processing (DSP), 1-5, 2018
FPGA-based evaluation of cryptographic algorithms
B Jungk
Universitätsbibliothek Johann Christian Senckenberg, 2015
On FPGA-based implementations of the SHA-3 candidate Grøstl
B Jungk, S Reith
2010 International Conference on Reconfigurable Computing and FPGAs, 316-321, 2010
There goes your pin: Exploiting smartphone sensor fusion under single and cross user setting
D Berend, S Bhasin, B Jungk
Proceedings of the 13th International Conference on Availability …, 2018
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