Sharad Sinha
Sharad Sinha
Indian Institute of Technology (IIT), Goa
Verified email at iitgoa.ac.in - Homepage
Title
Cited by
Cited by
Year
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications
J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 430-437, 2017
472017
Low-Power FPGA Design Using Memoization-Based Approximate Computing
S Sinha, W Zhang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (8 …, 2016
212016
Paas: A system level simulator for heterogeneous computing architectures
T Liang, L Feng, S Sinha, W Zhang
2017 27th International Conference on Field Programmable Logic and …, 2017
122017
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis
J Zhao, T Liang, S Sinha, W Zhang
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2019
112019
Extended compatibility path based hardware binding algorithm for area-time efficient designs
U Dhawan, S Sinha, SK Lam, T Srikanthan
2nd Asia Symposium on Quality Electronic Design (ASQED), 151-156, 2010
112010
Parallelizing Hardware Tasks on Multi-Context FPGA with Efficient Placement and Scheduling Algorithms
H Liang, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
92018
Heterosim: A heterogeneous cpu-fpga simulator
L Feng, H Liang, S Sinha, W Zhang
IEEE Computer Architecture Letters 16 (1), 38-41, 2017
82017
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA
J Zhao, L Feng, S Sinha, W Zhang, Y Liang, B He
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
72019
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power
Z Lin, S Sinha, W Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
72018
Understanding industrial espionage for greater technological and economic security
S Sinha
IEEE Potentials 31 (3), 37-41, 2012
72012
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm
H Liang, S Sinha, R Warrier, W Zhang
2015 25th International Conference on Field Programmable Logic and …, 2015
62015
FinTech: The New Frontier
S Sinha
IEEE Potentials 36 (6), 6-7, 2017
52017
Advanced/Smart Manufacturing: From Nanoscale to Megascale
S Sinha
IEEE Potentials 35 (4), 7-8, 2016
52016
Analytical delay model for CPU-FPGA data paths in programmable system-on-chip FPGA
M Tahghighi, S Sinha, W Zhang
Proceedings of the 12th International Symposium on Applied Reconfigurable …, 2016
52016
High-level synthesis: Boosting designer productivity and reducing time to market
S Sinha, T Srikanthan
IEEE Potentials 34 (4), 31-35, 2015
52015
Dataflow graph partitioning for area-efficient high-level synthesis with systems perspective
S Sinha, T Srikanthan
ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014
52014
Dataflow graph partitioning for high level synthesis
S Sinha, T Srikanthan
22nd International Conference on Field Programmable Logic and Applications …, 2012
52012
A novel binding algorithm to reduce critical path delay during high level synthesis
S Sinha, U Dhawan, SK Lam, T Srikanthan
2011 IEEE Computer Society Annual Symposium on VLSI, 278-283, 2011
52011
Using the clock period constraint to your advantage
S Sinha
Xcell Journal 77, 46-49, 2011
42011
Smart Nation: Indoor Navigation for the Visually Impaired
LB Leng, KG Smitha, S Sinha
2019 4th International Conference on Intelligent Transportation Engineering …, 2019
32019
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