| QNoC: QoS architecture and design process for network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Journal of systems architecture 50 (2-3), 105-128, 2004 | 763 | 2004 |
| TEAM: Threshold adaptive memristor model S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE transactions on circuits and systems I: regular papers 60 (1), 211-221, 2012 | 586 | 2012 |
| Interconnect-power dissipation in a microprocessor N Magen, A Kolodny, U Weiser, N Shamir Proceedings of the 2004 international workshop on System level interconnect …, 2004 | 543 | 2004 |
| MAGIC—Memristor-aided logic S Kvatinsky, D Belousov, S Liman, G Satat, N Wald, EG Friedman, ... IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 895-899, 2014 | 404 | 2014 |
| Memristor-based material implication (IMPLY) logic: Design principles and methodologies S Kvatinsky, G Satat, N Wald, EG Friedman, A Kolodny, UC Weiser IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (10 …, 2013 | 393 | 2013 |
| VTEAM: A general model for voltage-controlled memristors S Kvatinsky, M Ramadan, EG Friedman, A Kolodny IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 786-790, 2015 | 358 | 2015 |
| Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors TY Morad, UC Weiser, A Kolodnyt, M Valero, E Ayguade IEEE Computer Architecture Letters 5 (1), 14-17, 2006 | 251 | 2006 |
| Analysis and modeling of floating-gate EEPROM cells A Kolodny, STK Nieh, B Eitan, J Shappir IEEE Transactions on Electron Devices 33 (6), 835-844, 1986 | 211 | 1986 |
| MRL—Memristor ratioed logic S Kvatinsky, N Wald, G Satat, A Kolodny, UC Weiser, EG Friedman 2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012 | 210 | 2012 |
| Memristor-based multilayer neural networks with online gradient descent training D Soudry, D Di Castro, A Gal, A Kolodny, S Kvatinsky IEEE transactions on neural networks and learning systems 26 (10), 2408-2421, 2015 | 198 | 2015 |
| HNOCS: modular open-source simulator for heterogeneous NoCs Y Ben-Itzhak, E Zahavi, I Cidon, A Kolodny 2012 international conference on embedded computer systems (SAMOS), 51-57, 2012 | 133 | 2012 |
| Memristor-based IMPLY logic design procedure S Kvatinsky, A Kolodny, UC Weiser, EG Friedman 2011 IEEE 29th International Conference on Computer Design (ICCD), 142-147, 2011 | 131 | 2011 |
| Many-core vs. many-thread machines: Stay away from the valley Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser IEEE Computer Architecture Letters 8 (1), 25-28, 2009 | 131 | 2009 |
| Cost considerations in network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Integration 38 (1), 19-42, 2004 | 127 | 2004 |
| The power of priority: NoC based distributed cache coherency E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007 | 100 | 2007 |
| Routing table minimization for irregular mesh NoCs E Bolotin, I Cidon, R Ginosar, A Kolodny 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 90 | 2007 |
| Effective radii of on-chip decoupling capacitors M Popovich, M Sotman, A Kolodny, EG Friedman IEEE Transactions on very large scale integration (VLSI) systems 16 (7), 894-907, 2008 | 89 | 2008 |
| Efficient link capacity and QoS design for network-on-chip Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 89 | 2006 |
| Two components of tunneling current in metal‐oxide‐semiconductor structures B Eitan, A Kolodny Applied Physics Letters 43 (1), 106-108, 1983 | 84 | 1983 |
| QNoC asynchronous router RR Dobkin, R Ginosar, A Kolodny Integration 42 (2), 103-115, 2009 | 82 | 2009 |
Eby G. FriedmanDistinguished Professor, University of RochesterVerified email at ece.rochester.edu
