| A Formal Foundation for Secure Remote Execution of Enclaves P Subramanyan, R Sinha, I Lebedev, S Devadas, S Seshia ACM CCS 2017, 2017 | 163 | 2017 |
| Moat: Verifying Confidentiality of Enclave Programs R Sinha, S Rajamani, SA Seshia, K Vaswani ACM CCS 2015, 1169-1184, 2015 | 154 | 2015 |
| A design and verification methodology for secure isolated regions R Sinha, M Costa, A Lal, NP Lopes, S Rajamani, SA Seshia, K Vaswani Proceedings of the 37th ACM SIGPLAN Conference on Programming Language …, 2016 | 83 | 2016 |
| Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs R Sinha, A Prakash, HD Patel Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific …, 2012 | 65 | 2012 |
| A compiler and verifier for page access oblivious computation R Sinha, S Rajamani, SA Seshia Proceedings of the 2017 11th Joint Meeting on Foundations of Software …, 2017 | 38 | 2017 |
| VeritasDB: High Throughput Key-Value Store with Integrity R Sinha, M Christodorescu | 36 | 2018 |
| Automatic rootcausing for program equivalence failures in binaries SK Lahiri, R Sinha, C Hawblitzel International Conference on Computer Aided Verification, 362-379, 2015 | 25 | 2015 |
| Amortized Threshold Symmetric-key Encryption M Christodorescu, S Gaddam, P Mukherjee, R Sinha ACM CCS 2021, 2021 | 17 | 2021 |
| hinTS: Threshold Signatures with Silent Setup S Garg, A Jain, P Mukherjee, R Sinha, M Wang, Y Zhang IEEE S&P 2024, 2024 | 15 | 2024 |
| LucidiTEE: A TEE-Blockchain System for Policy-Compliant Multiparty Computation with Fairness R Sinha, S Gaddam, R Kumaresan | 14* | |
| Threshold Signatures in the Multiverse L Baird, S Garg, A Jain, P Mukherjee, R Sinha, M Wang, Y Zhang IEEE S&P 2023, 2023 | 12 | 2023 |
| Cryptography with Weights: MPC, Encryption and Signatures S Garg, A Jain, P Mukherjee, R Sinha, M Wang, Y Zhang CRYPTO 2023, 2023 | 12 | 2023 |
| i-TiRE: Incremental Timed-Release Encryption or How to use Timed-Release Encryption on Blockchains? L Baird, P Mukherjee, R Sinha CCS 2022, 2022 | 12* | 2022 |
| Verification of Quantitative Hyperproperties Using Trace Enumeration Relations S Sahai, R Sinha, P Subramanyan arXiv preprint arXiv:2005.04606, 2020 | 12 | 2020 |
| synASM: A high-level synthesis framework with support for parallel and timed constructs R Sinha, HD Patel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012 | 11 | 2012 |
| Abstract state machines as an intermediate representation for high-level synthesis R Sinha, HD Patel Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, 1-6, 2011 | 11 | 2011 |
| : Sublinear Prover AR Choudhuri, S Garg, A Goel, S Sekar, R Sinha Privacy Enhancing Technologies Symposium 2024, 2024 | 10* | 2024 |
| Verification with small and short worlds R Sinha, C Sturton, P Maniatis, SA Seshia, D Wagner Formal Methods in Computer-Aided Design (FMCAD), 2012, 68-77, 2012 | 9 | 2012 |
| Techniques for preventing collusion using simultaneous key release S Gaddam, R Kumaresan, R Sinha US Patent App. 17/296,510, 2022 | 8 | 2022 |
| A User’s Guide to UCLID Version 3.1 BA Brady, SA Seshia, R Sinha, SK Lahiri, RE Bryant | 6 | 2015 |
Sanjit A. SeshiaProfessor of EECS, University of California, BerkeleyVerified email at eecs.berkeley.edu
