| Design analysis of XOR (4T) based low voltage CMOS full adder circuit S Wairya, G Singh, RK Nagaria, S Tiwari 2011 Nirma University International Conference on Engineering, 1-7, 2011 | 71 | 2011 |
| Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design S Wairya, RK Nagaria, S Tiwari VLSI Design 2012, 7-7, 2012 | 70 | 2012 |
| Comparative performance analysis of XORXNOR function based high-speed CMOS full adder circuits for low voltage VLSI design S Wairya, RK Nagaria, S Tiwari International Journal of VLSI Design & Communication Systems 3 (2), 221, 2012 | 67 | 2012 |
| A novel design of quantum dot cellular automata 5-input majority gate with some physical proofs SR Kassa, RK Nagaria Journal of Computational Electronics 15, 324-334, 2016 | 48 | 2016 |
| New design methodologies for high speed low power XOR-XNOR circuits SS Mishra, S Wairya, RK Nagaria, S Tiwari World Academy of Science, Engineering and Technology 55, 200-206, 2009 | 45 | 2009 |
| New design methodologies for high-speed mixed-mode CMOS full adder circuits S Wairya, RK Nagaria, S Tiwari International Journal of VLSI design & Communication Systems (VLSICS) 2 (2 …, 2011 | 43 | 2011 |
| Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load AK Dubey, RK Nagaria Microelectronics Journal 78, 1-10, 2018 | 42 | 2018 |
| Energy efficient neoteric design of a 3-input majority gate with its implementation and physical proof in quantum dot cellular automata SR Kassa, RK Nagaria, R Karthik Nano communication networks 15, 28-40, 2018 | 41 | 2018 |
| Design and analysis of ultra high-speed low-power double tail dynamic comparator using charge sharing scheme V Varshney, RK Nagaria AEU-International Journal of Electronics and Communications 116, 153068, 2020 | 39 | 2020 |
| DFAL: diode-free adiabatic logic circuits S Upadhyay, RA Mishra, RK Nagaria, SP Singh International Scholarly Research Notices 2013, 2013 | 34 | 2013 |
| A new mixed gate diffusion input full adder topology for high speed low power digital circuits AK Agrawal, S Wairya, RK Nagaria, S Tiwari World Applied Science Journal 7, 138-144, 2009 | 34 | 2009 |
| 3D geographical routing protocols in wireless ad hoc and sensor networks: An overview NK Gupta, RS Yadav, RK Nagaria Wireless Networks 26, 2549-2566, 2020 | 33 | 2020 |
| Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage AK Dubey, RK Nagaria Analog Integrated Circuits and Signal Processing 101 (2), 307-317, 2019 | 26 | 2019 |
| New design methodologies for high-speed low-voltage 1 bit CMOS Full Adder circuits S Wairya, RK Nagaria, S Tiwari International Journal of Computer Technology and Application 2 (3), 190-198, 2011 | 26 | 2011 |
| Ultra low voltage high speed 1-bit CMOS adder S Wairya, H Pandey, RK Nagaria, S Tiwari 2010 International Conference on Power, Control and Embedded Systems, 1-6, 2010 | 23 | 2010 |
| A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits A Kumar, RK Nagaria Integration 63, 174-184, 2018 | 22 | 2018 |
| Low power dynamic buffer circuits AK Pandey, RA Mishra, RK Nagaria International Journal of VLSI Design & Communication Systems 3 (5), 53, 2012 | 20 | 2012 |
| Proposing a novel low-power high-speed mixed GDI full adder topology AK Agrawal, S Mishra, RK Nagaria 2010 International Conference on Power, Control and Embedded Systems, 1-6, 2010 | 20 | 2010 |
| Power efficiency improvement in OFDM system using SLM with adaptive nonlinear estimator PK Sharma, RK Nagaria, TN Sharma World Applied Sciences Journal 7, 145-151, 2009 | 20 | 2009 |
| Enhanced gain low-power CMOS amplifiers: a novel design approach using bulk-driven load and introduction to GACOBA technique AK Dubey, RK Nagaria Journal of Circuits, Systems and Computers 27 (13), 1850204, 2018 | 19 | 2018 |
