| Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4≤ m≤ 10) compressors S Mehrabi, RF Mirzaee, S Zamanzadeh, K Navi, O Hashemipour International Journal of High Performance Systems Architecture 4 (4), 231-241, 2013 | 27 | 2013 |
| Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering S Zamanzadeh, A Jahanian 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration …, 2013 | 12 | 2013 |
| Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology S Zamanzadeh, A Jahanian Microprocessors and Microsystems 42, 1-9, 2016 | 10 | 2016 |
| Multiplication With :2 and :3 Compressors—A Comparative Review S Mehrabi, RF Mirzaee, S Zamanzadeh, A Jamalian Canadian Journal of Electrical and Computer Engineering 40 (4), 303-313, 2017 | 9 | 2017 |
| A new hybrid 16-bit—16bit multiplier architecture by m: 2 and m: 3 compressors S Mehrabi, RF Mirzaee, S Zamanzadeh, A Jamalian International Journal of Information and Electronics Engineering 6 (2), 79, 2016 | 6 | 2016 |
| ASIC Design Protection against Reverse Engineering during the Fabrication Process using Automatic Netlist Obfuscation Design Flow. S Zamanzadeh, A Jahanian ISeCure 8 (2), 2016 | 5 | 2016 |
| Security path: An emerging design methodology to protect the fpga ips against passive/active design tampering S Zamanzadeh, A Jahanian Journal of Electronic Testing 32, 329-343, 2016 | 5 | 2016 |
| Security improvement of FPGA configuration file against the reverse engineering attack S ZamanZadeh, S Shahabi, A Jahanian 2016 13th International Iranian Society of Cryptology Conference on …, 2016 | 4 | 2016 |
| Pre-synthesis optimization for asynchronous circuits using compiler techniques S ZamanZadeh, M Najibi, H Pedram Advances in Computer Science and Engineering: 13th International CSI …, 2009 | 3 | 2009 |
| Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers S Zamanzadeh, A Jahanian 2017 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), 85-90, 2017 | 2 | 2017 |
| Self Authentication Path Insertion in FPGA-based Design Flow for Tamper-resistant Purpose S Zamanzadeh, A Jahanian THE ISC INTERNATIONAL JOURNAL OF INFORMATION SECURITY 8 (1), 53-60, 2016 | 1 | 2016 |
| ISeCure S Zamanzadeh, A Jahanian | | 2016 |
| Reimbursing the handshake overhead of asynchronous circuits using compiler pre-synthesis optimizations S ZamanZadeh, M Mirza-Aghatabar, M Najibi, H Pedram, A Sadeghi 2008 11th EUROMICRO Conference on Digital System Design Architectures …, 2008 | | 2008 |
Shima Mehrabiislamic azad universityVerified email at ieee.org
Shima Mehrabiislamic azad universityVerified email at ieee.org