allon adir
allon adir
Researcher, IBM Research Labs Haifa
Verified email at
Cited by
Cited by
Genesys-pro: Innovations in test program generation for functional processor verification
A Adir, E Almog, L Fournier, E Marcus, M Rimon, M Vinov, A Ziv
IEEE Design & Test of Computers 21 (2), 84-93, 2004
A unified methodology for pre-silicon verification and post-silicon validation
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, ...
2011 Design, Automation & Test in Europe, 1-6, 2011
Modeling language and method for address translation design mechanisms in test generation
A Koyfman, A Adir, R Emek, Y Katz, M Vinov
US Patent 7,370,296, 2008
Reaching coverage closure in post-silicon validation
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Haifa Verification Conference, 60-75, 2010
Information-flow models for shared memory with an application to the PowerPC architecture
A Adir, H Attiya, G Shurek
IEEE transactions on parallel and distributed systems 14 (5), 502-515, 2003
Threadmill: a post-silicon exerciser for multi-threaded processors
A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv
Proceedings of the 48th Design Automation Conference, 860-865, 2011
Non-unique results in design verification by test programs
A Adir
US Patent 8,055,492, 2011
Highly specialized scenarios in random test generation
A Adir, R Emek, I Jaeger, E Marcus, T Schechner
US Patent 7,434,101, 2008
DC inductive shorted patch antenna
WE McKinzie III, GS Mendolia, J Dutton
US Patent 6,882,316, 2005
Generating concurrent test-programs with collisions for multi-processor verification
A Adir, G Shurek
Seventh IEEE International High-Level Design Validation and Test Workshop …, 2002
Piparazzi: a test program generator for micro-architecture flow verification
A Adir, E Bin, O Peled, A Ziv
Eighth IEEE International High-Level Design Validation and Test Workshop, 23-28, 2003
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
A Adir, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Proceedings of the 48th Design Automation Conference, 569-574, 2011
Model-based hardware exerciser, device, system and method thereof
A Adir, GE Shurek
US Patent 7,945,888, 2011
Verification of transactional memory in power8
A Adir, D Goodman, D Hershcovich, O Hershkovitz, B Hickerson, K Holtz, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
Automatic test program generation using extended conditional constraint satisfaction
A Adir, E Bin, R Emek, K Shoikhet
US Patent 7,386,521, 2008
Advances in simultaneous multithreading testcase generation methods
JM Ludden, M Rimon, BG Hickerson, A Adir
Haifa Verification Conference, 146-160, 2010
Systematic compliance checking of a process
A Adir, S Asaf, L Fournier, I Jaeger, O Peled
US Patent 7,673,261, 2010
Adaptive test program generation
A Adir, R Emek, E Marcus
US Patent 6,925,405, 2005
Test quality through resource reallocation
A Adir, E Marcus, M Rimon, A Voskoboynik
US Patent 7,133,816, 2006
DeepTrans-a model-based approach to functional verification of address translation mechanisms
A Adir, R Emek, Y Katz, A Koyfman
Proceedings. 4th International Workshop on Microprocessor Test and …, 2003
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