| 2D materials: roadmap to CMOS integration C Huyghebaert, T Schram, Q Smets, TK Agarwal, D Verreck, S Brems, ... 2018 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2018 | 94 | 2018 |
| Ultra-scaled MOCVD MoS2 MOSFETs with 42nm contact pitch and 250µA/µm drain current IR Quentin Smets, Goutham Arutchelvan , Julien Jussot , Devin Verreck , Inge ... 2019 IEEE International Electron Devices Meeting (IEDM), 2019 | 81 | 2019 |
| From the metal to the channel: A study of carrier injection through the metal/2D MoS 2 interface G Arutchelvan, CJL de la Rosa, P Matagne, S Sutar, I Radu, ... Nanoscale 9 (30), 10869-10879, 2017 | 74 | 2017 |
| MoS2 Functionalization with a Sub-nm Thin SiO2 Layer for Atomic Layer Deposition of High-κ Dielectrics H Zhang, G Arutchelvan, J Meersschaut, A Gaur, T Conard, H Bender, ... Chemistry of Materials 29 (16), 6772-6780, 2017 | 39 | 2017 |
| Impact of device scaling on the electrical properties of MoS2 field-effect transistors G Arutchelvan, Q Smets, D Verreck, Z Ahmed, A Gaur, S Sutar, J Jussot, ... Scientific reports 11 (1), 6610, 2021 | 37 | 2021 |
| Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab I Asselberghs, Q Smets, T Schram, B Groven, D Verreck, A Afzalian, ... 2020 IEEE International Electron Devices Meeting (IEDM), 40.2. 1-40.2. 4, 2020 | 36 | 2020 |
| Introducing 2D-FETs in device scaling roadmap using DTCO Z Ahmed, A Afzalian, T Schram, D Jang, D Verreck, Q Smets, ... 2020 IEEE International Electron Devices Meeting (IEDM), 22.5. 1-22.5. 4, 2020 | 35 | 2020 |
| Reactive plasma cleaning and restoration of transition metal dichalcogenide monolayers D Marinov, JF de Marneffe, Q Smets, G Arutchelvan, KM Bal, E Voronina, ... npj 2D Materials and Applications 5 (1), 17, 2021 | 32 | 2021 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 32 | 2020 |
| Insight on the characterization of MoS2 based devices and requirements for logic device integration CJL de la Rosa, G Arutchelvan, I Radu, D Lin, C Huyghebaert, M Heyns, ... ECS Journal of Solid State Science and Technology 5 (11), Q3072, 2016 | 32 | 2016 |
| The Role of Nonidealities in the Scaling of MoS2 FETs D Verreck, G Arutchelvan, CJL De La Rosa, A Leonhardt, D Chiappe, ... IEEE Transactions on Electron Devices 65 (10), 4635-4640, 2018 | 21 | 2018 |
| Enabling logic with backside connectivity via n-TSVs and its potential as a scaling booster A Veloso, A Jourdain, G Hiblot, F Schleicher, K D’have, F Sebaai, ... 2021 Symposium on VLSI Technology, 1-2, 2021 | 17 | 2021 |
| Graphene based Van der Waals contacts on MoS2 field effect transistors V Mootheri, G Arutchelvan, S Banerjee, S Sutar, A Leonhardt, ME Boulon, ... 2D Materials 8 (1), 015003, 2020 | 17 | 2020 |
| Sources of variability in scaled MoS2 FETs Q Smets, D Verreck, Y Shi, G Arutchelvan, B Groven, X Wu, S Sutar, ... 2020 IEEE International Electron Devices Meeting (IEDM), 3.1. 1-3.1. 4, 2020 | 16 | 2020 |
| Buried power rail integration with Si FinFETs for CMOS scaling beyond the 5 nm node A Gupta, H Mertens, Z Tao, S Demuynck, J Bömmels, G Arutchelvan, ... 2020 IEEE Symposium on VLSI Technology, 1-2, 2020 | 16 | 2020 |
| Transport properties of chemically synthesized MoS2–Dielectric effects and defects scattering M Mongillo, D Chiappe, G Arutchelvan, I Asselberghs, M Perucchini, ... Applied Physics Letters 109 (23), 2016 | 16 | 2016 |
| IEEE International Electron Devices Meeting (IEDM) Q Smets, G Arutchelvan, J Jussot, D Verreck, I Asselberghs, AN Mehta, ... IEEE, 2019 | 13 | 2019 |
| Relation between film thickness and surface doping of MoS2 based field effect transistors CJ Lockhart de la Rosa, G Arutchelvan, A Leonhardt, C Huyghebaert, ... Apl Materials 6 (5), 2018 | 13 | 2018 |
| 2018 IEEE Int. Electron Devices Meeting (IEDM) C Huyghebaert, T Schram, Q Smets, TK Agarwal, D Verreck, S Brems, ... IEEE, 2018 | 12 | 2018 |
| Scaled FinFETs connected by using both wafer sides for routing via buried power rails A Veloso, A Jourdain, D Radisic, R Chen, G Arutchelvan, B O’Sullivan, ... IEEE Transactions on Electron Devices 69 (12), 7173-7179, 2022 | 11 | 2022 |
Dennis Han Chung LinIMECVerified email at imec.be
