Pierre - Emmanuel GAILLARDON
Pierre - Emmanuel GAILLARDON
Associate Professor, University of Utah
Verified email at utah.edu - Homepage
Title
Cited by
Cited by
Year
Advances, challenges and opportunities in 3D CMOS sequential integration
P Batude, M Vinet, B Previtali, C Tabone, C Xu, J Mazurier, O Weber, ...
2011 International Electron Devices Meeting, 7.3. 1-7.3. 4, 2011
2812011
3-D sequential integration: A key enabling technology for heterogeneous co-integration of new function with CMOS
P Batude, T Ernst, J Arcamone, G Arndt, P Coudrain, PE Gaillardon
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2 (4á…, 2012
2422012
Polarity control in double-gate, gate-all-around vertically stacked silicon nanowire FETs
M De Marchi, D Sacchetto, S Frache, J Zhang, PE Gaillardon, Y Leblebici, ...
2012 International Electron Devices Meeting, 8.4. 1-8.4. 4, 2012
2382012
Majority-inverter graph: A novel data-structure and algorithms for efficient logic optimization
L Amar˙, PE Gaillardon, G De Micheli
2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2014
1492014
Can we go towards true 3-D architectures?
PE Gaillardon, H Ben-Jamaa, PH Morel, JP NoŰl, F Clermidy, I O'Connor
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), 282-283, 2011
1432011
Majority-inverter graph: A new paradigm for logic optimization
L Amaru, PE Gaillardon, G De Micheli
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2015
1422015
The EPFL combinational benchmark suite
L Amar˙, PE Gaillardon, G De Micheli
Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS), 2015
1382015
The programmable logic-in-memory (PLiM) computer
PE Gaillardon, L Amar˙, A Siemon, E Linn, R Waser, A Chattopadhyay, ...
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 427-432, 2016
1202016
Configurable logic gates using polarity-controlled silicon nanowire gate-all-around FETs
M De Marchi, J Zhang, S Frache, D Sacchetto, PE Gaillardon, Y Leblebici, ...
IEEE Electron Device Letters 35 (8), 880-882, 2014
812014
Emerging technology-based design of primitives for hardware security
Y Bi, K Shamsi, JS Yuan, PE Gaillardon, GD Micheli, X Yin, XS Hu, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (1), 1-19, 2016
682016
Top–down fabrication of gate-all-around vertically stacked silicon nanowire FETs with controllable polarity
M De Marchi, D Sacchetto, J Zhang, S Frache, PE Gaillardon, Y Leblebici, ...
IEEE transactions on Nanotechnology 13 (6), 1029-1038, 2014
682014
Doping-free complementary logic gates enabled by two-dimensional polarity-controllable transistors
GV Resta, Y Balaji, D Lin, IP Radu, F Catthoor, PE Gaillardon, ...
ACS nano 12 (7), 7039-7047, 2018
642018
Polarity control in WSe 2 double-gate transistors
GV Resta, S Sutar, Y Balaji, D Lin, P Raghavan, I Radu, F Catthoor, ...
Scientific reports 6 (1), 1-6, 2016
642016
Leveraging emerging technology for hardware security-case study on silicon nanowire fets and graphene symfets
Y Bi, PE Gaillardon, XS Hu, M Niemier, JS Yuan, Y Jin
2014 IEEE 23rd Asian Test Symposium, 342-347, 2014
632014
Polarity-controllable silicon nanowire transistors with dual threshold voltages
J Zhang, M De Marchi, D Sacchetto, PE Gaillardon, Y Leblebici, ...
IEEE Transactions on Electron Devices 61 (11), 3654-3660, 2014
632014
Configurable circuits featuring dual-threshold-voltage design with three-independent-gate silicon nanowire FETs
J Zhang, X Tang, PE Gaillardon, G De Micheli
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (10), 2851-2861, 2014
612014
Energy/reliability trade-offs in low-voltage ReRAM-based non-volatile flip-flop design
I Kazi, P Meinerzhagen, PE Gaillardon, D Sacchetto, Y Leblebici, A Burg, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (11), 3155-3164, 2014
602014
Design and architectural assessment of 3-d resistive memory technologies in fpgas
PE Gaillardon, D Sacchetto, GB Beneventi, MHB Jamaa, L Perniola, ...
IEEE Transactions on Nanotechnology 12 (1), 40-50, 2012
572012
Emerging memory technologies for reconfigurable routing in FPGA architecture
PE Gaillardon, MH Ben-Jamaa, GB Beneventi, F Clermidy, L Perniola
2010 17th IEEE International Conference on Electronics, Circuits and Systemsá…, 2010
572010
Fast logic synthesis for RRAM-based in-memory computing using majority-inverter graphs
S Shirinzadeh, M Soeken, PE Gaillardon, R Drechsler
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 948-953, 2016
562016
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