QNoC: QoS architecture and design process for network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Journal of systems architecture 50 (2-3), 105-128, 2004 | 814 | 2004 |
Fourteen ways to fool your synchronizer R Ginosar Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003 | 315 | 2003 |
Metastability and synchronizers: A tutorial R Ginosar IEEE Design & Test of Computers 28 (5), 23-35, 2011 | 236 | 2011 |
Relative timing [asynchronous design] KS Stevens, R Ginosar, S Rotem Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 11 (1 …, 2003 | 232 | 2003 |
A random access photodiode array for intelligent image capture O Yadid-Pecht, R Ginosar, Y Shacham-Diamand IEEE transactions on electron devices 38 (8), 1772-1780, 1991 | 217 | 1991 |
An efficient implementation of Boolean functions as self-timed circuits I David, R Ginosar, M Yoeli IEEE transactions on computers 41 (01), 2-11, 1992 | 197 | 1992 |
Data synchronization issues in GALS SoCs R Dobkin, R Ginosar, CP Sotiriou 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004 | 182 | 2004 |
Multiple wireless communication protocol methods and apparatuses R Nevo, E Zehavi, BA Monello, R Ginosar US Patent 6,600,726, 2003 | 181 | 2003 |
An asynchronous router for multiple service levels networks on chip D Rostislav, V Vishnyakov, E Friedman, R Ginosar 11th IEEE international symposium on asynchronous circuits and systems, 44-53, 2005 | 170 | 2005 |
An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection Y Perelman, R Ginosar IEEE Transactions on biomedical engineering 54 (1), 130-137, 2006 | 167* | 2006 |
Cost considerations in network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny INTEGRATION, the VLSI journal 38 (1), 19-42, 2004 | 140 | 2004 |
Color wide dynamic range camera R Ginosar, O Zinaty, N Sorek, T Genossar, YY Zeevi, DJ Kligler US Patent 5,247,366, 1993 | 136 | 1993 |
Intelligent scan image sensor YY Zeevi, RG Ar, O Hilsenrath US Patent 4,942,473, 1990 | 117 | 1990 |
Resistive associative processor L Yavits, S Kvatinsky, A Morad, R Ginosar IEEE Computer Architecture Letters 14 (2), 148-151, 2014 | 116 | 2014 |
RAPPID: An asynchronous instruction length decoder S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ... Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings …, 1999 | 116 | 1999 |
An asynchronous instruction length decoder KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ... IEEE Journal of solid-state circuits 36 (2), 217-228, 2001 | 115 | 2001 |
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders R Dobkin, M Peleg, R Ginosar IEEE transactions on very large scale integration (VLSI) systems 13 (4), 427-438, 2005 | 112* | 2005 |
The power of priority: NoC based distributed cache coherency E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007 | 104 | 2007 |
The effect of communication and synchronization on Amdahl’s law in multicore systems L Yavits, A Morad, R Ginosar Parallel Computing 40 (1), 1-16, 2014 | 103 | 2014 |
A resistive CAM processing-in-storage architecture for DNA sequence alignment R Kaplan, L Yavits, R Ginosar, U Weiser IEEE Micro 37 (4), 20-28, 2017 | 101 | 2017 |