| QNoC: QoS architecture and design process for network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Journal of systems architecture 50 (2-3), 105-128, 2004 | 763 | 2004 |
| Fourteen ways to fool your synchronizer R Ginosar Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003 | 290 | 2003 |
| A random access photodiode array for intelligent image capture O Yadid-Pecht, R Ginosar, Y Shacham-Diamand IEEE transactions on electron devices 38 (8), 1772-1780, 1991 | 195 | 1991 |
| Relative timing [asynchronous design] KS Stevens, R Ginosar, S Rotem Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 11 (1 …, 2003 | 194 | 2003 |
| Metastability and synchronizers: A tutorial R Ginosar IEEE Design & Test of Computers 28 (5), 23-35, 2011 | 183 | 2011 |
| An efficient implementation of Boolean functions as self-timed circuits I David, R Ginosar, M Yoeli IEEE Computer Architecture Letters 41 (01), 2-11, 1992 | 182 | 1992 |
| Multiple wireless communication protocol methods and apparatuses R Nevo, E Zehavi, BA Monello, R Ginosar US Patent 6,600,726, 2003 | 177 | 2003 |
| Data synchronization issues in GALS SoCs R Dobkin, R Ginosar, CP Sotiriou 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004 | 174 | 2004 |
| An asynchronous router for multiple service levels networks on chip D Rostislav, V Vishnyakov, E Friedman, R Ginosar 11th IEEE international symposium on asynchronous circuits and systems, 44-53, 2005 | 162 | 2005 |
| An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection Y Perelman, R Ginosar IEEE Transactions on biomedical engineering 54 (1), 130-137, 2006 | 150* | 2006 |
| Color wide dynamic range camera R Ginosar, O Zinaty, N Sorek, T Genossar, YY Zeevi, DJ Kligler US Patent 5,247,366, 1993 | 130 | 1993 |
| Cost considerations in network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny INTEGRATION, the VLSI journal 38 (1), 19-42, 2004 | 127 | 2004 |
| RAPPID: An asynchronous instruction length decoder S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ... Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings …, 1999 | 108 | 1999 |
| An asynchronous instruction length decoder KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ... IEEE Journal of solid-state circuits 36 (2), 217-228, 2001 | 105 | 2001 |
| Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders R Dobkin, M Peleg, R Ginosar IEEE transactions on very large scale integration (VLSI) systems 13 (4), 427-438, 2005 | 104* | 2005 |
| The power of priority: NoC based distributed cache coherency E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007 | 100 | 2007 |
| Intelligent scan image sensor YY Zeevi, RG Ar, O Hilsenrath US Patent 4,942,473, 1990 | 95 | 1990 |
| Timing measurements of synchronization circuits Y Semiat, R Ginosar Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003 | 94 | 2003 |
| Routing table minimization for irregular mesh NoCs E Bolotin, I Cidon, R Ginosar, A Kolodny 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 90 | 2007 |
| Efficient link capacity and QoS design for network-on-chip Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 89 | 2006 |
