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Ran Ginosar
Ran Ginosar
Professor of EE & CS, Technion
Verified email at ee.technion.ac.il - Homepage
Title
Cited by
Cited by
Year
QNoC: QoS architecture and design process for network on chip
E Bolotin, I Cidon, R Ginosar, A Kolodny
Journal of systems architecture 50 (2-3), 105-128, 2004
7922004
Fourteen ways to fool your synchronizer
R Ginosar
Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003
3002003
A random access photodiode array for intelligent image capture
O Yadid-Pecht, R Ginosar, Y Shacham-Diamand
IEEE transactions on electron devices 38 (8), 1772-1780, 1991
2091991
Relative timing [asynchronous design]
KS Stevens, R Ginosar, S Rotem
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 11 (1 …, 2003
2072003
Metastability and synchronizers: A tutorial
R Ginosar
IEEE Design & Test of Computers 28 (5), 23-35, 2011
1962011
An efficient implementation of Boolean functions as self-timed circuits
I David, R Ginosar, M Yoeli
IEEE transactions on computers 41 (01), 2-11, 1992
1861992
Multiple wireless communication protocol methods and apparatuses
R Nevo, E Zehavi, BA Monello, R Ginosar
US Patent 6,600,726, 2003
1792003
Data synchronization issues in GALS SoCs
R Dobkin, R Ginosar, CP Sotiriou
10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004
1752004
An asynchronous router for multiple service levels networks on chip
D Rostislav, V Vishnyakov, E Friedman, R Ginosar
11th IEEE international symposium on asynchronous circuits and systems, 44-53, 2005
1632005
An integrated system for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection
Y Perelman, R Ginosar
IEEE Transactions on biomedical engineering 54 (1), 130-137, 2006
156*2006
Color wide dynamic range camera
R Ginosar, O Zinaty, N Sorek, T Genossar, YY Zeevi, DJ Kligler
US Patent 5,247,366, 1993
1341993
Cost considerations in network on chip
E Bolotin, I Cidon, R Ginosar, A Kolodny
INTEGRATION, the VLSI journal 38 (1), 19-42, 2004
1332004
RAPPID: An asynchronous instruction length decoder
S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ...
Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings …, 1999
1121999
An asynchronous instruction length decoder
KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ...
IEEE Journal of solid-state circuits 36 (2), 217-228, 2001
1052001
Intelligent scan image sensor
YY Zeevi, RG Ar, O Hilsenrath
US Patent 4,942,473, 1990
1051990
The power of priority: NoC based distributed cache coherency
E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny
First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007
1022007
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
R Dobkin, M Peleg, R Ginosar
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (4), 427-438, 2005
102*2005
The effect of communication and synchronization on Amdahl’s law in multicore systems
L Yavits, A Morad, R Ginosar
Parallel Computing 40 (1), 1-16, 2014
972014
Routing table minimization for irregular mesh NoCs
E Bolotin, I Cidon, R Ginosar, A Kolodny
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
932007
Timing measurements of synchronization circuits
Y Semiat, R Ginosar
Ninth International Symposium on Asynchronous Circuits and Systems, 2003 …, 2003
922003
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