Sushanta K. Mandal
Title
Cited by
Cited by
Year
ANN-and PSO-based synthesis of on-chip spiral inductors for RF ICs
SK Mandal, S Sural, A Patra
IEEE transactions on computer-aided design of integrated circuits and …, 2007
912007
Low power multiplier architectures using vedic mathematics in 45nm technology for high speed computing
BSP Suryasnata Tripathy, L B Omprakash, Sushanta K. Mandal
Communication, Information & Computing Technology (ICCICT), 2015 …, 2015
18*2015
A wide-band lumped element compact CAD model of Si-based planar spiral inductor for RFIC design
SK Mandal, A De, A Patra, S Sural
19th International Conference on VLSI Design held jointly with 5th …, 2006
112006
A comparative analysis of different 8-bit adder topologies at 45 nm technology
S Tripathy, LB Omprakash, BS Patro, SK Mandal
International journal of engineering research and technology 2 (10), 2013
92013
Analysis of daylighting using daylight factor and luminance for different room scenarios
BN Mohapatra, MR Kumar, SK Mandal
International Journal of Civil Engineering and Technology (IJCIET) 9 (10 …, 2018
82018
A 6–17 GHz linear wide tuning range and low power ring oscillator in 45nm CMOS process for electronic warfare
BS Patro, JK Panigrahi, SK Mandal
2012 International Conference on Communication, Information & Computing …, 2012
82012
An efficient power clock generation circuit for complementary pass-transistor adiabatic logic carry-save multiplier
P Ranjith, SK Mandal, D Nagchoudhuri
2009 4th International Conference on Computers and Devices for Communication …, 2009
82009
Low power, high speed full adder architectures in 45nm technology
S Tripathy, LB Omprakash, BS Patro, SK Mandal
International conference on VLSI and signal processing, IIT Kharagpur, 2014
72014
High speed low power datapath design using multi threshold logic in 45 nm technology for signsl processing application
S Tripathy, SK Mandal
National Conference on VLSI Signal Processing and Trends in …, 2014
62014
FGMOS based low-voltage low-power high output impedance regulated cascode current mirror
A Anand, SK Mandal, A Dash, BS Patro
International Journal of VLSI Design & Communication Systems 4 (2), 39, 2013
62013
Swarm optimization based on-chip inductor optimization
SK Mandal, A Goyel, A Gupta
2009 4th International Conference on Computers and Devices for Communication …, 2009
62009
Low Power FGSRAM Cell Using Sleepy and LECTOR Technique
KB Ray, SK Mandal, BS Patro
Indonesian Journal of Electrical Engineering and Computer Science 4 (2), 333-340, 2016
52016
A high speed CMOS current comparator in 90 nm CMOS process technology
A Rath, SK Mandal, S Das, SP Dash
International Journal of Computer Applications 975, 8887, 2014
52014
Reconfigurable antennas and their applications
HC Mohanta, A Kouzani, SK Mandal
Universal Journal of Electrical and Electronic Engineering 6 (4), 239-258, 2019
42019
A flipped voltage follower based analog multiplier in 90nm CMOS process
A Satapathy, SK Maity, SK Mandal
2015 International Conference on Advances in Computer Engineering and …, 2015
42015
Design of Ultra Low Power LC VCO in 45 nm standart CMOS Process
A Sahu, SK Mandal
IJCA Proceedings on International Conference on Communication, Circuits and …, 2012
42012
A 6 bit 800MHz TIADC based on Successive Approximation in 65nm Standard CMOS Process
A Salimath, C Debnath, K Chatterjee, SK Mandal
2010 23rd International Conference on VLSI Design, 312-317, 2010
42010
Particle swarm optimization for modeling and parameter extraction of on-chip spiral inductors for RFICs
SK Mandal, A De, A Patra, S Sural, TK Bhattacharya
Proceedings of the IEEE INDICON 2004. First India Annual Conference, 2004 …, 2004
42004
Positioning of light shelves to enhance daylight illuminance in office rooms
BN Mohapatra, MR Kumar, SK Mandal
Indonesian Journal of Electrical Engineering and Computer Science 15 (1 …, 2019
32019
Notice of Removal: High speed Square Root Carry Select Adder using MTCMOS D-Latch in 45nm technology
A Das, SK Mandal, JK Das
2015 International Conference on Electrical, Electronics, Signals …, 2015
32015
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