Yibo Chen
Yibo Chen
Ph.D. of Computer Engineering, Penn State University
Verified email at cse.psu.edu - Homepage
Title
Cited by
Cited by
Year
Test-access mechanism optimization for core-based three-dimensional SOCs
X Wu, Y Chen, K Chakrabarty, Y Xie
Microelectronics Journal 41 (10), 601-615, 2010
1252010
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis
Y Chen, D Niu, Y Xie, K Chakrabarty
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 471-476, 2010
722010
3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory
Y Chen, J Zhao, Y Xie
Proceedings of the 16th ACM/IEEE international symposium on Low powerá…, 2010
532010
Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs
Y Chen, E Kursun, D Motschman, C Johnson, Y Xie
IEEE/ACM International Symposium on Low Power Electronics and Design, 397-402, 2011
382011
Arithmetic unit design using 180nm TSV-based 3D stacking technology
J Ouyang, G Sun, Y Chen, L Duan, T Zhang, Y Xie, MJ Irwin
2009 IEEE International Conference on 3D System Integration, 1-4, 2009
352009
Variation-aware task and communication mapping for mpsoc architecture
F Wang, Y Chen, C Nicopoulos, X Wu, Y Xie, N Vijaykrishnan
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2011
332011
Through silicon via aware design planning for thermally efficient 3-D integrated circuits
Y Chen, E Kursun, D Motschman, C Johnson, Y Xie
IEEE Transactions on Computer-Aided Design of Integrated Circuits andá…, 2013
232013
Tolerating process variations in high-level synthesis using transparent latches
Y Chen, Y Xie
2009 Asia and South Pacific Design Automation Conference, 73-78, 2009
232009
Design and implementation of a wifi-based local locating system
Y Chen, R Luo
2007 IEEE International Conference on Portable Information Devices, 1-5, 2007
202007
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment
Y Chen, Y Xie, Y Wang, A Takach
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 689-694, 2010
162010
Statistical high-level synthesis under process variability
Y Xie, Y Chen
IEEE Design & Test of Computers 26 (4), 78-87, 2009
152009
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs
Y Chen, G Sun, Q Zou, Y Xie
2012 Design, Automation & Test in Europe Conference & Exhibition (DATEá…, 2012
82012
ILP-based scheme for timing variation-aware scheduling and resource binding
Y Chen, J Ouyang, Y Xie
2008 IEEE International SOC Conference, 27-30, 2008
82008
Three-dimensional integrated circuits: Design, eda, and architecture
G Sun, Y Chen, X Dong, J Ouyang, Y Xie
Foundations and Trends« in Electronic Design Automation 5 (1–2), 1-151, 2011
72011
Energy and performance driven circuit design for emerging Phase-Change Memory
D Niu, Y Chen, X Dong, Y Xie
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 193-198, 2010
42010
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Y Chen, Y Xie, Y Wang, A Takach
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 781-786, 2010
42010
System-level design space exploration for three-dimensional (3D) SoCs
Q Zou, Y Chen, Y Xie, A Su
Proceedings of the seventh IEEE/ACM/IFIP international conference oná…, 2011
32011
Test-access solutions for three-dimensional SOCs
X Wu, Y Chen, K Chakrabarty, Y Xie
2008 IEEE International Test Conference, 1-1, 2008
32008
A system level fine-grained dynamic voltage and frequency scaling for portable embedded systems with multiple frequency adjustable components
K He, Y Chen, R Luo
2007 IEEE International Conference on Portable Information Devices, 1-5, 2007
32007
Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizing
Y Chen, Y Wang, Y Xie, A Takach
Journal of Electrical and Computer Engineering 2012, 2012
12012
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Articles 1–20