Ronny Ronen
Ronny Ronen
Technion, Haifa, Israel; EE department
Verified email at
Cited by
Cited by
Distribution of processing activity across processing hardware based on power consumption considerations
D Orenstien, R Ronen
US Patent 6,804,632, 2004
Speculation techniques for improving load related instruction scheduling
A Yoaz, M Erez, R Ronen, S Jourdan
Proceedings of the 26th annual international symposium on Computer …, 1999
Coming challenges in microarchitecture and architecture
R Ronen, A Mendelson, K Lai, SL Lu, F Pollack, JP Shen
Proceedings of the IEEE 89 (3), 325-340, 2001
Method and apparatus for varying energy per instruction according to the amount of available parallelism
E Grochowski, J Shen, H Wang, D Orenstein, GS Sheaffer, R Ronen, ...
US Patent 7,437,581, 2008
Best of both latency and throughput
E Grochowski, R Ronen, J Shen, H Wang
IEEE International Conference on Computer Design: VLSI in Computers and …, 2004
A novel renaming scheme to exploit value temporal locality through physical register reuse and unification
S Jourdan, R Ronen, M Bekerman, B Shomar, A Yoaz
Proceedings. 31st Annual ACM/IEEE International Symposium on …, 1998
Distribution of processing activity in a multiple core microprocessor
D Orenstien, R Ronen
US Patent 7,043,405, 2006
Correlated load-address predictors
M Bekerman, S Jourdan, R Ronen, G Kirshenboim, L Rappoport, A Yoaz, ...
ACM SIGARCH Computer Architecture News 27 (2), 54-63, 1999
Programming model for a heterogeneous x86 platform
B Saha, X Zhou, H Chen, Y Gao, S Yan, M Rajagopalan, J Fang, P Zhang, ...
Proceedings of the 30th ACM SIGPLAN Conference on Programming Language …, 2009
Micro-operation cache: a power aware frontend for the variable instruction length isa
B Solomon, A Mendelson, D Orenstein, Y Almog, R Ronen
Proceedings of the 2001 international symposium on Low power electronics and …, 2001
Method and system for branch target prediction using path information
L Rappoport, R Ronen, N Kacevas, O Lempel
US Patent 6,601,161, 2003
SIMPLER MAGIC: Synthesis and mapping of in-memory logic executed in a single row to improve throughput
R Ben-Hur, R Ronen, A Haj-Ali, D Bhattacharjee, A Eliahu, N Peled, ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
Low-power processor hint, such as from a PAUSE instruction
D Orenstien, R Ronen
US Patent 6,687,838, 2004
Power management for multiple processor cores
L Finkelstein, E Rotem, A Cohen, R Ronen, D Rajwan
US Patent 8,402,290, 2013
On estimating optimal performance of cpu dynamic thermal management
A Cohen, F Finkelstein, A Mendelson, R Ronen, D Rudoy
IEEE Computer Architecture Letters 2 (1), 6-6, 2003
System and method for fusing instructions
R Ronen, A Peleg, N Hoffman
US Patent 6,675,376, 2004
Deterministic power-estimation for thermal control
D Orenstien, R Ronen
US Patent 7,096,145, 2006
Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history
G Kedem, R Ronen, A Yoaz
US Patent 6,134,643, 2000
Early load address resolution via register tracking
M Bekerman, A Yoaz, F Gabbay, S Jourdan, M Kalaev, R Ronen
ACM SIGARCH Computer Architecture News 28 (2), 306-315, 2000
Imaging: In-memory algorithms for image processing
A Haj-Ali, R Ben-Hur, N Wald, R Ronen, S Kvatinsky
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4258-4271, 2018
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