Soumya Pandit, M.Sc, M.Tech, Ph.D., MIE(I), SMIEEE
Soumya Pandit, M.Sc, M.Tech, Ph.D., MIE(I), SMIEEE
Assistant Professor, Stage-III, Institute of Radio Physics and Electronics, University of Calcutta
Verified email at caluniv.ac.in - Homepage
Title
Cited by
Cited by
Year
Technology computer aided design: simulation for VLSI MOSFET
CK Sarkar
CRC Press, 2013
352013
Nano-scale CMOS analog circuits: models and CAD techniques for high-level design
S Pandit, C Mandal, A Patra
CRC Press, 2018
212018
INSECT MOULTING HORMONE, ECDYSTERONE FROM SIDA CARPINIFOLIA LINN.
SS Pandit, N SD
141976
Modeling and design of a nano scale cmos inverter for symmetric switching characteristics
J Mukhopadhyay, S Pandit
VLSI Design 2012, 2012
122012
Systematic methodology for high-level performance modeling of analog systems
S Pandit, C Mandal, A Patra
2009 22nd International Conference on VLSI Design, 361-366, 2009
112009
Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor
S Sengupta, S Pandit
International Journal of Electronics 102 (6), 967-981, 2015
92015
Fringing Capacitance based surface potential model for pocket DMG n-MOSFETs
S De, A Sarkar, CK Sarkar
Journal of Electron Devices 12, 704-712, 2012
92012
Channel Profile Design ofDC MOSFET for High Intrinsic Gain and LowMismatch
S Sengupta, S Pandit
IEEE Transactions on Electron Devices 63 (2), 551-557, 2016
72016
Study of analog and RF performance of UTB-OI-Si substrate MOS transistor using buffered InGaAs and Silicon channel
SK Maity, S Pandit
2015 6th International conference on computers and devices for communication …, 2015
72015
A fast exploration procedure for analog high-level specification translation
S Pandit, SK Bhattacharya, C Mandal, A Patra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008
72008
Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET
SK Maity, S Pandit
International Journal of Electronics 104 (11), 1777-1794, 2017
62017
Design of a Nano-scale CMOS Inverter with Symmetric Switching Characteristics using Particle Swarm Optimization Algorithm
J Mukhopadhyay, S Pandit
IEMCON, 0
6*
Study of GS/D underlap for enhanced analog performance and RF/circuit analysis of UTB InAs-OI-Si MOSFET using NQS small signal model
SK Maity, S Pandit
Superlattices and Microstructures 101, 362-372, 2017
52017
Adaptive sampling algorithm for ANN-based performance modeling of nano-scale CMOS inverter
D Dhabak, S Pandit
World Acad Sci Eng Technol 80, 812-818, 2011
52011
A methodology for generation of performance models for the sizing of analog high-level topologies
S Pandit, C Mandal, A Patra
VLSI Design 2011, 2011
42011
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count
S Pandit, S Kar, C Mandal, A Patra
Proceedings of the Design Automation & Test in Europe Conference 1, 1-2, 2006
42006
Analysis of Drain Current Local Variability of an n-Channel E DC MOSFET Due to RDD Considering Inversion Charge and Correlated Mobility Fluctuations
S Sengupta, S Pandit
IEEE Transactions on Electron Devices 65 (4), 1267-1275, 2018
32018
Study of temperature variation on threshold voltage and sub-threshold slope of E δ DC MOS transistor including quantum corrections and …
R Das, AK Gond, S Sengupta, RR Sahani, S Pandit
Microsystem Technologies 23 (9), 4221-4229, 2017
32017
Substrate bias effect of epitaxial delta-doped channel MOS transistor for low-power applications
S Sengupta, S Sikdar, S Pandit
International Journal of Electronics 104 (1), 47-63, 2017
32017
An artificial neural network-based approach for performance modeling of nano-scale cmos inverter
D Dhabak, S Pandit
Institute of Engineering and Management Conference, 165-170, 2011
32011
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