| Negative-resistance read and write schemes for STT-MRAM in 0.13 µm CMOS D Halupka, S Huda, W Song, A Sheikholeslami, K Tsunoda, C Yoshida, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 256-257, 2010 | 115 | 2010 |
| Clock gating architectures for FPGA power reduction S Huda, M Mallick, JH Anderson 2009 International Conference on Field Programmable Logic and Applications …, 2009 | 84 | 2009 |
| A full-stack search technique for domain optimized deep learning accelerators D Zhang, S Huda, E Songhori, K Prabhu, Q Le, A Goldie, A Mirhoseini Proceedings of the 27th ACM International Conference on Architectural …, 2022 | 55 | 2022 |
| A survey on circuit modeling of spin-transfer-torque magnetic tunnel junctions A Vatankhahghadim, S Huda, A Sheikholeslami IEEE Transactions on Circuits and Systems I: Regular Papers 61 (9), 2634-2643, 2014 | 48 | 2014 |
| On hard adders and carry chains in FPGAs J Luu, C McCullough, S Wang, S Huda, B Yan, C Chiasson, KB Kent, ... 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014 | 48 | 2014 |
| A novel STT-MRAM cell with disturbance-free read operation S Huda, A Sheikholeslami IEEE Transactions on Circuits and Systems I: Regular Papers 60 (6), 1534-1547, 2013 | 43 | 2013 |
| Optimizing FPGA logic block architectures for arithmetic KE Murray, J Luu, MJP Walker, C McCullough, S Wang, S Huda, B Yan, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (6 …, 2020 | 20 | 2020 |
| Hybrid LUT/Multiplexer FPGA logic architectures SA Chin, J Luu, S Huda, JH Anderson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (4 …, 2015 | 17 | 2015 |
| Optimizing effective interconnect capacitance for FPGA power reduction S Huda, J Anderson, H Tamura Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014 | 14 | 2014 |
| Charge recycling for power reduction in FPGA interconnect S Huda, J Anderson, H Tamura 2013 23rd International Conference on Field programmable Logic and …, 2013 | 14 | 2013 |
| Leveraging unused resources for energy optimization of FPGA interconnect S Huda, JH Anderson IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (8 …, 2017 | 11 | 2017 |
| A full-stack accelerator search technique for vision applications D Zhang, S Huda, E Songhori, Q Le, A Goldie, A Mirhoseini arXiv preprint arXiv:2105.12842, 2021 | 8 | 2021 |
| Towards PVT-tolerant glitch-free operation in FPGAs S Huda, J Anderson Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 8 | 2016 |
| Learning to design accurate deep learning accelerators with inaccurate multipliers P Jain, S Huda, M Maas, JE Gonzalez, I Stoical, A Mirhoseini 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 184-189, 2022 | 4 | 2022 |
| Resiliency at Scale: Managing {Google’s}{TPUv4} Machine Learning Supercomputer Y Zu, A Ghaffarkhah, HV Dang, B Towles, S Hand, S Huda, A Bello, ... 21st USENIX Symposium on Networked Systems Design and Implementation (NSDI …, 2024 | 3 | 2024 |
| Circuits, Architectures, and CAD for Low-Power FPGAs S Huda University of Toronto (Canada), 2017 | 3 | 2017 |
| Power optimization of FPGA interconnect via circuit and CAD techniques S Huda, JH Anderson Proceedings of the 2016 on International Symposium on Physical Design, 123-130, 2016 | 3 | 2016 |
| Modeling and Design of Spin Torque Transfer Magnetoresistive Random Access Memory S Huda | 2 | 2012 |
| Large-Scale Accelerator System Energy Performance Optimization MD Hutton, G Konstadinidis, LM Munguia, H Safeen, G Agrawal US Patent App. 17/968,048, 2023 | 1 | 2023 |
| Optimizing off-chip memory accesses on a neural network hardware accelerator D Zhang, H Safeen, A Mirhoseini, AD Goldie, E Songhori US Patent App. 18/285,977, 2024 | | 2024 |
