Amir Nahir
Title
Cited by
Cited by
Year
A unified methodology for pre-silicon verification and post-silicon validation
A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, ...
2011 Design, Automation & Test in Europe, 1-6, 2011
702011
Bridging pre-silicon verification and post-silicon validation
A Nahir, A Ziv, M Abramovici, A Camilleri, R Galivanche, B Bentley, ...
Design Automation Conference, 94-95, 2010
492010
Reaching coverage closure in post-silicon validation
A Adir, A Nahir, A Ziv, C Meissner, J Schumann
Haifa Verification Conference, 60-75, 2010
432010
Threadmill: a post-silicon exerciser for multi-threaded processors
A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv
Proceedings of the 48th Design Automation Conference, 860-865, 2011
392011
On cost-aware monitoring for self-adaptive load sharing
D Breitgand, R Cohen, A Nahir, D Raz
IEEE Journal on Selected Areas in communications 28 (1), 70-83, 2009
372009
Topology design and control: A game-theoretic perspective
A Nahir, A Orda, A Freund
IEEE INFOCOM 2009, 1620-1628, 2009
322009
Replication-based load balancing
A Nahir, A Orda, D Raz
IEEE Transactions on Parallel and Distributed Systems 27 (2), 494-507, 2015
292015
Computer Aided Verification: 26th International Conference, CAV 2014, Held as Part of the Vienna Summer of Logic, VSL 2014, Vienna, Austria, July 18-22, 2014, Proceedings
A Biere, R Bloem
Springer, 2014
272014
Workload factoring with the cloud: A game-theoretic perspective
A Nahir, A Orda, D Raz
2012 Proceedings IEEE INFOCOM, 2566-2570, 2012
272012
Post-silicon validation of the IBM POWER8 processor
A Nahir, M Dusanapudi, S Kapoor, K Reick, W Roesner, KD Schubert, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
232014
Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor
A Adir, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann
Proceedings of the 48th Design Automation Conference, 569-574, 2011
232011
TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead
FM de Paula, A Nahir, Z Nevo, A Orni, AJ Hu
Proceedings of the 48th Design Automation Conference, 411-416, 2011
232011
Topology design of communication networks: A game-theoretic perspective
A Nahir, A Orda, A Freund
IEEE/ACM Transactions on Networking 22 (2), 405-414, 2013
222013
Verification of transactional memory in power8
A Adir, D Goodman, D Hershcovich, O Hershkovitz, B Hickerson, K Holtz, ...
Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014
192014
Dynamic selection of trace signals for post-silicon debug
K Basu, P Mishra, P Patra, A Nahir, A Adir
2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013
182013
Optimizing test-generation to the execution platform
A Nahir, A Ziv, S Panda
17th Asia and South Pacific Design Automation Conference, 304-309, 2012
142012
nuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces
FM De Paula, AJ Hu, A Nahir
International Conference on Computer Aided Verification, 513-531, 2012
132012
Resource allocation and management in cloud computing
A Nahir, A Orda, D Raz
2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015
112015
Hardware verification using acceleration platform
M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ...
US Patent 8,832,502, 2014
112014
Schedule first, manage later: Network-aware load balancing
A Nahir, A Orda, D Raz
2013 Proceedings IEEE INFOCOM, 510-514, 2013
112013
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Articles 1–20