| A unified methodology for pre-silicon verification and post-silicon validation A Adir, S Copty, S Landa, A Nahir, G Shurek, A Ziv, C Meissner, ... 2011 Design, Automation & Test in Europe, 1-6, 2011 | 92 | 2011 |
| Bridging pre-silicon verification and post-silicon validation A Nahir, A Ziv, R Galivanche, A Hu, M Abramovici, A Camilleri, B Bentley, ... Proceedings of the 47th Design Automation Conference, 94-95, 2010 | 59 | 2010 |
| Threadmill: A post-silicon exerciser for multi-threaded processors A Adir, M Golubev, S Landa, A Nahir, G Shurek, V Sokhin, A Ziv Proceedings of the 48th Design Automation Conference, 860-865, 2011 | 53 | 2011 |
| Reaching coverage closure in post-silicon validation A Adir, A Nahir, A Ziv, C Meissner, J Schumann Haifa Verification Conference, 60-75, 2010 | 52 | 2010 |
| On cost-aware monitoring for self-adaptive load sharing D Breitgand, R Cohen, A Nahir, D Raz IEEE Journal on Selected Areas in communications 28 (1), 70-83, 2009 | 46 | 2009 |
| Replication-based load balancing A Nahir, A Orda, D Raz IEEE Transactions on Parallel and Distributed Systems 27 (2), 494-507, 2015 | 44 | 2015 |
| TAB-BackSpace: Unlimited-length trace buffers with zero additional on-chip overhead FM De Paula, A Nahir, Z Nevo, A Orni, AJ Hu Proceedings of the 48th Design Automation Conference, 411-416, 2011 | 37 | 2011 |
| Topology design and control: A game-theoretic perspective A Nahir, A Orda, A Freund IEEE INFOCOM 2009, 1620-1628, 2009 | 33 | 2009 |
| Post-silicon validation of the IBM POWER8 processor A Nahir, M Dusanapudi, S Kapoor, K Reick, W Roesner, KD Schubert, ... Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 30 | 2014 |
| Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor A Adir, A Nahir, G Shurek, A Ziv, C Meissner, J Schumann Proceedings of the 48th Design Automation Conference, 569-574, 2011 | 30 | 2011 |
| Workload factoring with the cloud: A game-theoretic perspective A Nahir, A Orda, D Raz 2012 Proceedings IEEE INFOCOM, 2566-2570, 2012 | 29 | 2012 |
| Topology design of communication networks: A game-theoretic perspective A Nahir, A Orda, A Freund IEEE/ACM Transactions on Networking 22 (2), 405-414, 2013 | 28 | 2013 |
| Verification of transactional memory in power8 A Adir, D Goodman, D Hershcovich, O Hershkovitz, B Hickerson, K Holtz, ... Proceedings of the 51st Annual Design Automation Conference, 1-6, 2014 | 27 | 2014 |
| Dynamic selection of trace signals for post-silicon debug K Basu, P Mishra, P Patra, A Nahir, A Adir 2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013 | 25 | 2013 |
| Optimizing test-generation to the execution platform A Nahir, A Ziv, S Panda 17th Asia and South Pacific Design Automation Conference, 304-309, 2012 | 19 | 2012 |
| Hardware verification using acceleration platform M Dusanapudi, W Kadry, S Kapoor, D Krestyashyn, S Landa, A Nahir, ... US Patent 8,832,502, 2014 | 18 | 2014 |
| Resource allocation and management in cloud computing A Nahir, A Orda, D Raz 2015 IFIP/IEEE International Symposium on Integrated Network Management (IM …, 2015 | 17 | 2015 |
| nuTAB-BackSpace: Rewriting to normalize non-determinism in post-silicon debug traces FM De Paula, AJ Hu, A Nahir International Conference on Computer Aided Verification, 513-531, 2012 | 16 | 2012 |
| Control flow error localization O Friedler, W Kadry, A Nahir, V Sokhin US Patent 9,251,045, 2016 | 15 | 2016 |
| Random test generation using an optimization solver A Nahir, Y Shiloach US Patent 7,530,036, 2009 | 15 | 2009 |
Avi ZivResearch Staff Member, IBMVerified email at il.ibm.com
