| A high performance D-flip flop design with low power clocking system using MTCMOS technique P Dobriyal, K Sharma, M Sethi, G Sharma 2013 3rd IEEE International Advance Computing Conference (IACC), 1524-1528, 2013 | 25 | 2013 |
| A novel high performance dual threshold voltage domino logic employing stacked transistors M Sethi, K Sharma, P Dobriyal, N Rajput, G Sharma International Journal of Computer Applications 77 (5), 2013 | 11 | 2013 |
| A novel, high performance and power efficient implementation of 8× 8 multiplier unit using MT-CMOS technique N Rajput, M Sethi, P Dobriyal, K Sharma, G Sharma 2013 Sixth International Conference on Contemporary Computing (IC3), 186-191, 2013 | 10 | 2013 |
| Designing a Novel Power Efficient D-Flip Flop using Forced Stack Technique K Sharma, M Sethi, P Dobriyal, G Sharma International Journal of Computer Applications 975, 8887, 2013 | 3 | 2013 |
| 1. FORUM ONE Standard specifications RV Lele, ML Sethi, PD Swami, KD Sharma, UN Nayak Bulletin 1, 2, 1954 | | 1954 |
| A Novel, High Performance and Power Efficient Implementation of Decimal to BCD Converter using 90nm Hybrid PTL/CMOS Technique N Rajput, M Sethi, K Sharma, P Dobriyal, G Sharma | | |
Geetanjali SharmaAssistant Professor of Electronics and Communication, GGSIPU, New DelhiVerified email at msit.in
