Shahar Kvatinsky

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Avinoam KolodnyProfessor of Electrical Engineering, TechnionVerified email at ee.technion.ac.il
Eby G. FriedmanDistinguished Professor, University of RochesterVerified email at ece.rochester.edu
Uri WeiserProfessor, TechnionVerified email at ee.technion.ac.il
Nimrod WaldTechnion, Israel institute of technologyVerified email at campus.technion.ac.il
Rotem Ben-HurTechnion - Israel Institute of TechnologyVerified email at campus.technion.ac.il
Guy SatatResearch Assistant, MITVerified email at mit.edu
Nishil TalatiPhD Student, CSE, University of MichiganVerified email at umich.edu
Ameer Haj-AliPh.D., Electrical Engineering and Computer Science, UC BerkeleyVerified email at berkeley.edu
Nicolás WainsteinTechnion - Israel Institute of TechnologyVerified email at campus.technion.ac.il
Ronny RonenTechnion, Haifa, Israel; EE departmentVerified email at technion.ac.il
Daniel SoudryAssistant ProfessorVerified email at technion.ac.il
Loai DanialTechnionVerified email at campus.technion.ac.il
Eitan YaakobiAssociate Professor at TechnionVerified email at cs.technion.ac.il
Yuval CassutoDeptartment of Electrical Engineering, TechnionVerified email at ee.technion.ac.il
Pierre - Emmanuel GAILLARDONAssociate Professor, University of UtahVerified email at utah.edu
Dotan Di CastroBosch Center for AI, Haifa, IsraelVerified email at bosch.com
Ran GinosarProfessor of EE & CS, TechnionVerified email at ee.technion.ac.il
Mark HorowitzProfessor of Electrical Engineering and Computer ScienceVerified email at ee.stanford.edu
Stephen E. RichardsonResearch Associate, Stanford UniversityVerified email at stanford.edu
Ardavan PedramStanford UniversityVerified email at stanford.edu

Shahar Kvatinsky

Technion - Israel Institute of Technology

Verified email at ee.technion.ac.il - Homepage

Memristor Memristive systems VLSI RRAM neuromorphic


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TEAM: Threshold adaptive memristor model S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE transactions on circuits and systems I: regular papers 60 (1), 211-221, 2012	594	2012
MAGIC–memristor aided LoGIC S Kvatinsky, D Belousov, S Liman, G Satat, N Wald, EG Friedman, ... IEEE Transactions on Circuits and Systems II: Express Briefs 61 (11), 895 - 899, 2014	416	2014
Memristor-based material implication (imply) logic: Design principles and methodologies S Kvatinsky, G Satat, N Wald, EG Friedman, A Kolodny, UC Weiser IEEE Transaction on VLSI 22 (10), 2054 - 2066, 2014	401	2014
VTEAM: A general model for voltage-controlled memristors S Kvatinsky, M Ramadan, EG Friedman, A Kolodny IEEE Transactions on Circuits and Systems II: Express Briefs 62 (8), 786-790, 2015	371	2015
MRL—Memristor ratioed logic S Kvatinsky, N Wald, G Satat, A Kolodny, UC Weiser, EG Friedman 2012 13th International Workshop on Cellular Nanoscale Networks and their …, 2012	215	2012
Memristor-based multilayer neural networks with online gradient descent training D Soudry, D Di Castro, A Gal, A Kolodny, S Kvatinsky IEEE transactions on neural networks and learning systems 26 (10), 2408-2421, 2015	206	2015
Logic design within memristive memories using memristor-aided loGIC (MAGIC) N Talati, S Gupta, P Mane, S Kvatinsky IEEE Transactions on Nanotechnology 15 (4), 635-650, 2016	190	2016
Memristor-based IMPLY Logic Design Procedure S Kvatinsky, A Kolodny, UC Weiser, EG Friedman ICCD, 2011	133	2011
Models of memristors for SPICE simulations S Kvatinsky, K Talisveyberg, D Fliter, A Kolodny, UC Weiser, EG Friedman 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, 1-5, 2012	104*	2012
Sneak-path constraints in memristor crossbar arrays Y Cassuto, S Kvatinsky, E Yaakobi 2013 IEEE International Symposium on Information Theory, 156-160, 2013	89	2013
Logic operations in memory using a memristive Akers array Y Levy, J Bruck, Y Cassuto, EG Friedman, A Kolodny, E Yaakobi, ... Microelectronics Journal 45 (11), 1429-1437, 2014	77	2014
Dark memory and accelerator-rich system optimization in the dark silicon era A Pedram, S Richardson, M Horowitz, S Galal, S Kvatinsky IEEE Design & Test 34 (2), 39-50, 2016	72	2016
Resistive associative processor L Yavits, S Kvatinsky, A Morad, R Ginosar IEEE Computer Architecture Letters 14 (2), 148-151, 2014	71	2014
The desired memristor for circuit designers S Kvatinsky, EG Friedman, A Kolodny, UC Weiser IEEE Circuits and Systems Magazine 13 (2), 17-22, 2013	70	2013
Memristor for computing: Myth or reality? S Hamdioui, S Kvatinsky, G Cauwenberghs, L Xie, N Wald, S Joshi, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017	63	2017
SIMPLE MAGIC: Synthesis and in-memory mapping of logic execution for memristor-aided logic RB Hur, N Wald, N Talati, S Kvatinsky 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 225-232, 2017	44	2017
Memristive logic: A framework for evaluation and comparison J Reuben, R Ben-Hur, N Wald, N Talati, AH Ali, PE Gaillardon, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017	44	2017
A systematic approach to blocking convolutional neural networks X Yang, J Pu, BB Rister, N Bhagdikar, S Richardson, S Kvatinsky, ... arXiv preprint arXiv:1606.04209, 2016	43	2016
Efficient algorithms for in-memory fixed point multiplication using magic A Haj-Ali, R Ben-Hur, N Wald, S Kvatinsky 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018	37	2018
Information-theoretic sneak-path mitigation in memristor crossbar arrays Y Cassuto, S Kvatinsky, E Yaakobi IEEE Transactions on Information Theory 62 (9), 4801-4813, 2016	36	2016

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