Qijing Jenny Huang
Qijing Jenny Huang
Verified email at berkeley.edu
Title
Cited by
Cited by
Year
FireSim: FPGA-accelerated cycle-exact scale-out system simulation in the public cloud
S Karandikar, H Mao, D Kim, D Biancolin, A Amid, D Lee, N Pemberton, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
522018
From software to accelerators with LegUp high-level synthesis
A Canis, J Choi, B Fort, R Lian, Q Huang, N Calagar, M Gort, JJ Qin, ...
2013 International Conference on Compilers, Architecture and Synthesis for …, 2013
522013
The effect of compiler optimizations on high-level synthesis for FPGAs
Q Huang, R Lian, A Canis, J Choi, R Xi, S Brown, J Anderson
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
482013
The effect of compiler optimizations on high-level synthesis-generated hardware
Q Huang, R Lian, A Canis, J Choi, R Xi, N Calagar, S Brown, J Anderson
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 8 (3), 1-26, 2015
372015
Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded fpgas
Y Yang, Q Huang, B Wu, T Zhang, L Ma, G Gambardella, M Blott, ...
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
362019
AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning
Q Huang, A Haj-Ali, W Moses, J Xiang, I Stoica, K Asanovic, J Wawrzynek
arXiv preprint arXiv:2003.00671, 2020
12*2020
Integrating NVIDIA deep learning accelerator (NVDLA) with RISC-V soc on firesim
F Farshchi, Q Huang, H Yun
2019 2nd Workshop on Energy Efficient Machine Learning and Cognitive …, 2019
122019
Fpga accelerated indel realignment in the cloud
L Wu, D Bruns-Smith, FA Nothaft, Q Huang, S Karandikar, J Le, A Lin, ...
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
62019
AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs
K Settaluri, A Haj-Ali, Q Huang, K Hakhamaneshi, B Nikolic
Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2020
22020
AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning
A Haj-Ali, Q Huang, W Moses, J Xiang, I Stoica, K Asanovic, J Wawrzynek
arXiv, arXiv: 1901.04615, 2019
22019
Centrifuge: Evaluating full-system HLS-generated heterogeneous-accelerator SoCs using FPGA-Acceleration
Q Huang, C Yarp, S Karandikar, N Pemberton, B Brock, L Ma, G Dai, ...
2*
Algorithm-hardware Co-design for Deformable Convolution
Q Huang, D Wang, Y Gao, Y Cai, Z Dong, B Wu, K Keutzer, J Wawrzynek
http://www.emc2-ai.org/assets/docs/neurips-19/emc2-neurips19-paper-10.pdf, 0
1*
CoDeNet: Algorithm-hardware Co-design for Deformable Convolution
Z Dong, D Wang, Q Huang, Y Gao, Y Cai, B Wu, K Keutzer, J Wawrzynek
arXiv preprint arXiv:2006.08357, 2020
2020
ProTuner: Tuning Programs with Monte Carlo Tree Search
A Haj-Ali, H Genc, Q Huang, W Moses, J Wawrzynek, K Asanović, I Stoica
arXiv preprint arXiv:2005.13685, 2020
2020
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors
F Farshchi, Q Huang, H Yun
2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS …, 2020
2020
Synthesis of program binaries into FPGA accelerators with runtime dependence validation
S Cheng, Q Huang, J Wawrzynek
2017 International Conference on Field Programmable Technology (ICFPT), 96-103, 2017
2017
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Articles 1–16