| Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET V Narendar, P Narware, V Bheemudu, B Sunitha Silicon 12, 2283-2291, 2020 | 25 | 2020 |
| A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance N Vadthiya, P Narware, V Bheemudu, B Sunitha AEU-International Journal of Electronics and Communications 127, 153459, 2020 | 18 | 2020 |
| Design and performance optimization of junctionless bottom spacer FinFET for digital/analog/RF applications at sub-5nm technology node S Valasa, KV Ramakrishna, N Vadthiya, S Bhukya, NB Rao, ... ECS Journal of Solid State Science and Technology 12 (1), 013004, 2023 | 11 | 2023 |
| Optimizing u-shape FinFETs for sub-5nm technology: performance analysis and device-to-circuit evaluation in digital and analog/radio frequency applications KV Ramakrishna, S Valasa, S Bhukya, N Vadthiya ECS Journal of Solid State Science and Technology 12 (9), 093007, 2023 | 7 | 2023 |
| Design optimization of junctionless bottom spacer tapered FinFET: Device to circuit level implementation S Bhukya, BR Nistala Microelectronics Journal 139, 105907, 2023 | 4 | 2023 |
| Investigation of short channel effects (SCEs) and analog/RF figure of merits (FOMs) of dual-material bottom-spacer ground-plane (DMBSGP) FinFET. Silicon 12: 2283–2291 V Narendar, P Narware, V Bheemudu, B Sunitha | 4 | 2020 |
| A Proposal for Optimization of Spacer Engineering at Sub-5-nm Technology Node for JL-TreeFET: A Device to Circuit Level Implementation R Andavarapu, S Bagati, S Valasa, VR Kotha, S Bhukya, SK Padhi, ... IEEE Transactions on Electron Devices, 2023 | 2 | 2023 |
| Performance investigation of FinFET structures: unleashing multi-gate control through design and simulation at the 7 nm technology node for next-generation electronic devices S Valasa, KV Ramakrishna, S Bhukya, P Narware, V Bheemudu, ... ECS Journal of Solid State Science and Technology 12 (11), 113012, 2023 | 1 | 2023 |
| Optimization of Sidewall Spacer Engineering at Sub-5 nm Technology Node For JL-Nanowire FET: Digital/Analog/RF/Circuit Perspective C Anguru, VK Aryasomayajula, VR Kotha, S Valasa, S Bhukya, ... ECS Journal of Solid State Science and Technology 13 (1), 013002, 2024 | | 2024 |
| Design Considerations into Circuit Applications for Structurally Optimised FinFET K Sarangam, S Valasa, PK Mudidhe, V Narendar, VR Kotha, S Bhukya, ... ECS Journal of Solid State Science and Technology 12 (12), 123007, 2023 | | 2023 |
| A Comparative Analysis of FinFET and Nanosheet FET based Circuits with Geometrical Parameter Variations at sub-5 nm technology node V Kothwal, S Valasa, VR Kotha, S Bhukya, N Vadthiya, B Vadthya 2023 IEEE 20th India Council International Conference (INDICON), 753-758, 2023 | | 2023 |
| Simulation of dual material ground plane bottom spacer FinFET P Narware, V Narendar | | 2018 |
Vadthiya NarendarNational Institute of Technology WarangalVerified email at nitw.ac.in
