| Hardware and software enabled implementation of power profile management instructions in system on chip R Kaushal, A Gangwar, VM Pusuluri, S Kumar US Patent 9,568,970, 2017 | 56 | 2017 |
| A Trimaran based framework for exploring the design space of VLIW ASIPs with coarse grain functional units B Middha, A Gangwar, A Kumar, M Balakrishnan, P Ienne Proceedings of the 15th international symposium on System Synthesis, 2-7, 2002 | 47 | 2002 |
| Verification low power collateral generation VM Pusuluri, S Patchamatla, R Kaushal, A Gangwar, S Kumar US Patent 9,785,732, 2017 | 31 | 2017 |
| Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures A Gangwar, M Balakrishnan, A Kumar ACM Transactions on Design Automation of Electronic Systems (TODAES) 12 (1 …, 2007 | 25 | 2007 |
| Specification for automatic power management of network-on-chip and system-on-chip A Gangwar, VM Pusuluri, P Kongetira, S Kumar US Patent 9,477,280, 2016 | 24 | 2016 |
| Automatic generation of power management sequence in a SoC or NoC A Gangwar, VM Pusuluri, P Kongetira, S Kumar US Patent 10,042,404, 2018 | 17 | 2018 |
| Evaluation of bus based interconnect mechanisms in clustered VLIW architectures A Gangwar, M Balakrishnan, PR Panda, A Kumar International Journal of Parallel Programming 35, 507-527, 2007 | 16 | 2007 |
| SoC synthesis with automatic hardware-software interface generation A Singh, A Chhabra, A Gangwar, BK Dwivedi, M Balakrishnan, A Kumar 16th International Conference on VLSI Design, 2003. Proceedings., 585-590, 2003 | 10 | 2003 |
| Integrated circuit design A Gangwar, NK Agarwal US Patent 10,318,243, 2019 | 9 | 2019 |
| Topology agnostic virtual channel assignment and protocol level deadlock avoidance in a network-on-chip A Gangwar, R Sreedharan, A Prasad, NK Agarwal, SH Gade 2021 58th ACM/IEEE Design Automation Conference (DAC), 61-66, 2021 | 7 | 2021 |
| Network-on-chip topology generation NK Agarwal, A Gangwar, HHVNA Prasad, R Sreedharan, NSH Gade US Patent 11,194,950, 2021 | 6 | 2021 |
| Network on-chip topology generation NK Agarwal, A Gangwar, HHVNA Prasad, R Sreedharan US Patent 10,817,627, 2020 | 5 | 2020 |
| Customizing Embedded Processors for Specific Applications, In proceedings of Recent Trends in Practice and Theory of Information Technology MK Jain, A Kumar, M Balakrishnan, A Gangwar Proc. of NRB Seminar, 10-11, 2005 | 5 | 2005 |
| Network-on-chip link size generation HHVNA Prasad, A Gangwar, NK Agarwal, R Sreedharan US Patent 11,050,672, 2021 | 4 | 2021 |
| An automated traffic generation framework for performance evaluation of networks-on-chip for real world use cases SH Gade, A Gangwar, A Prasad, NK Agarwal, R Sreedharan 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 4 | 2021 |
| Automated synthesis of custom networks-on-chip for real world applications A Gangwar, NK Agarwal, R Sreedharan, A Prasad, SH Gade, Z Xu Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 4 | 2020 |
| Traffic driven automated synthesis of network-on-chip from physically aware behavioral specification A Gangwar, Z Xu, NK Agarwal, R Sreedharan, A Prasad 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 122-127, 2019 | 4 | 2019 |
| Network-on-Chip topology generation NSH Gade, HHVNA Prasad, A Gangwar, NK Agarwal, R Sreedharan US Patent 11,329,690, 2022 | 3 | 2022 |
| Virtual channel assignment for topology constrained network-on-chip design NK Agarwal, Z Xu, A Gangwar US Patent 10,791,045, 2020 | 3 | 2020 |
| Network-on-chip topology generation HHVNA Prasad, NK Agarwal, A Gangwar, NSH Gade, R Sreedharan US Patent 11,310,169, 2022 | 2 | 2022 |
