| A Novel Co-design Methodology for Optimizing ESD Protection Device Using Layout Level Approach V Abhinav, DK Sinha, A Chatterjee, F Brewer 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 2 | 2016 |
| Enhancing potentiometric response of electrochemical sensor using modified ion-sensitive transistor V Abhinav, R Patkar, M Vinchurkar, TR Naik, MS Baghini ECSarXiv, 2019 | 1 | 2019 |
| Methodology for optimizing ESD protection for high speed LVDS based I/Os V Abhinav, A Chatterjee, DK Sinha, R Singh 2015 19th International Symposium on VLSI Design and Test, 1-5, 2015 | 1 | 2015 |
| Core-shell oxide nanoparticles and their biomedical applications V Abhinav, P Ranjan, A Mahapatra, V Belwanshi, V Kumar Oxides for Medical Applications, 197-232, 2023 | | 2023 |
| Design and Simulation Study of a Piezoelectric Microcantilever-Based Energy Harvester for Ambient Vibrations V Belwanshi, V Abhinav, V Kumar Advancement in Materials, Manufacturing and Energy Engineering, Vol. II …, 2022 | | 2022 |
| Enhancing Potentiometric Response Using Modified Ion Sensitive Transistor V Abhinav, R Patkar, M Vinchurkar, TR Naik, MS Baghini Electrochemical Society Meeting Abstracts 235, 2022-2022, 2019 | | 2019 |
| An In-Silico investigation into the Electrode Design in Impedance Flow Cytometry V. Abhinav, R. Patel, P. Deshpande COMSOL Conference 2019, Bangalore, 2019 | | 2019 |
| A Novel Capacitorless DRAM Cell Design Using Band-Gap Engineered Junctionless Double-Gate FET DK Sinha, A Chatterjee, V Abhinav, G Trivedi, V Koldyaev 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | | 2016 |
Dheeraj Kumar SinhaDepartment of Electronics and Communication Engineering, Indian Institute of Information TechnologyVerified email at iitg.ernet.in
