| Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress TA Brunner, VC Menon, CW Wong, O Gluschenkov, MP Belyansky, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 12 (4), 043002-043002, 2013 | 55 | 2013 |
| Overlay and semiconductor process control using a wafer geometry metric P Vukkadala, S Veeraraghavan, JK Sinha US Patent 9,354,526, 2016 | 36 | 2016 |
| Process-induced distortion prediction and feedforward and feedback correction of overlay errors P Vukkadala, H Chen, J Sinha, S Veeraraghavan US Patent 10,401,279, 2019 | 24 | 2019 |
| Impact of wafer geometry on CMP for advanced nodes P Vukkadala, KT Turner, JK Sinha Journal of the Electrochemical Society 158 (10), H1002, 2011 | 23 | 2011 |
| Characterization and mitigation of overlay error on silicon wafers with nonuniform stress T Brunner, V Menon, C Wong, N Felix, M Pike, O Gluschenkov, ... Optical Microlithography XXVII 9052, 242-253, 2014 | 22 | 2014 |
| System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking P Vukkadala, S Veeraraghavan, J Sinha, H Chen, M Kirk US Patent 9,430,593, 2016 | 19 | 2016 |
| Monitoring process-induced overlay errors through high-resolution wafer geometry measurements KT Turner, P Vukkadala, S Veeraraghavan, JK Sinha Metrology, Inspection, and Process Control for Microlithography XXVIII 9050 …, 2014 | 15 | 2014 |
| Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool H Chen, J Sinha, S Kamensky, S Veeraraghavan, P Vukkadala US Patent 9,546,862, 2017 | 14 | 2017 |
| Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices H Lee, J Lee, SM Kim, C Lee, S Han, M Kim, W Kwon, SK Park, ... Metrology, Inspection, and Process Control for Microlithography XXIX 9424 …, 2015 | 14 | 2015 |
| Determining local residual stresses from high resolution wafer geometry measurements J Gong, P Vukkadala, JK Sinha, KT Turner Journal of Vacuum Science & Technology B 31 (5), 2013 | 14 | 2013 |
| Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements P Vukkadala, J Sinha, JH Kim US Patent 9,779,202, 2017 | 11 | 2017 |
| Systems and methods of advanced site-based nanotopography for wafer surface metrology H Chen, S Kamensky, J Sinha, P Vukkadala US Patent 9,177,370, 2015 | 11 | 2015 |
| System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking P Vukkadala, S Veeraraghavan, J Sinha, H Chen, M Kirk US Patent 10,025,894, 2018 | 10 | 2018 |
| A study of reticle non-flatness induced image placement error contributions in EUV lithography S Raghunathan, O Wood, P Vukkadala, R Engelstad, B Lee, S Bouten, ... Extreme Ultraviolet (EUV) Lithography 7636, 296-305, 2010 | 9 | 2010 |
| Predictive wafer modeling based focus error prediction using correlations of wafers P Vukkadala, J Sinha, W Chang, K Rao US Patent 9,707,660, 2017 | 8 | 2017 |
| Patterned wafer geometry grouping for improved overlay control H Lee, S Han, J Woo, J Park, C Song, F Anis, P Vukkadala, S Jeon, ... Metrology, Inspection, and Process Control for Microlithography XXXI 10145 …, 2017 | 8 | 2017 |
| Using wafer geometry to improve scanner correction effectiveness for overlay control C MacNaughton, S Veeraraghavan, P Vukkadala, J Sinha, A Azordegan US Patent 9,029,810, 2015 | 8 | 2015 |
| Determination of local electrostatic forces for EUVL mask chucks G Kalkowski, T Peschel, S Risse, S Müller, RL Engelstad, JR Zeuske, ... Microelectronic engineering 87 (5-8), 1287-1289, 2010 | 8 | 2010 |
| Patterned wafer geometry measurements for semiconductor process controls P Vukkadala, J Sinha US Patent 10,576,603, 2020 | 7 | 2020 |
| Using Depth Mapping to realize Bokeh effect with a single camera Android device J Gong, R Liu, P Vukkadala EE368 Project Report, 2016 | 7 | 2016 |
